The Community for Technology Leaders
International Test Conference 2007 (2007)
Santa Clara, CA
Oct. 21, 2007 to Oct. 26, 2007
ISSN: 1089-3539
ISBN: 978-1-4244-1127-6
TABLE OF CONTENTS

[Front cover] (PDF)

pp. c1

Table of contents (PDF)

pp. iii-xiv

Keynote address (PDF)

pp. 12-15

Author index (PDF)

pp. 24-25

On-chip timing uncertainty measurements on IBM microprocessors (PDF)

R. Franch , IBM Research, Yorktown Heights, NY, USA
P. Restle , IBM Research, Yorktown Heights, NY, USA
N. James , IBM STG, Austin, TX, USA
W. Huott , IBM STG, Poughkeepsie, NY, USA
J. Friedrich , IBM STG, Austin, TX, USA
R. Dixon , IBM STG, Austin, TX, USA
S. Weitzel , IBM STG, Austin, TX, USA
K. Van Goor , IBM STG, Rochester, MN, USA
G. Salem , IBM STG, Burlington, VT, USA
pp. 1-7

Design for testability features of the SUN microsystems niagara2 CMP/CMT SPARC chip (PDF)

Robert Molyneaux , SUN Microsystems, 5300 Riata Park, Austin, Tx. 78727, USA
Tom Ziaja , SUN Microsystems, 5300 Riata Park, Austin, Tx. 78727, USA
Hong Kim , SUN Microsystems, 5300 Riata Park, Austin, Tx. 78727, USA
Shahryar Aryani , SUN Microsystems, 5300 Riata Park, Austin, Tx. 78727, USA
Sungbae Hwang , SUN Microsystems, 5300 Riata Park, Austin, Tx. 78727, USA
Alex Hsieh , SUN Microsystems, 5300 Riata Park, Austin, Tx. 78727, USA
pp. 1-8

Test cost reduction for the AMD™ Athlon processor using test partitioning (PDF)

Anuja Sehgal , One AMD Place, Sunnyvale, CA 94088, USA
Jeff Fitzgerald , One AMD Place, Sunnyvale, CA 94088, USA
Jeff Rearick , 2950 E. Harmony Road, Ft. Collins, CO 80528, USA
pp. 1-10

On ATPG for multiple aggressor crosstalk faults in presence of gate delays (PDF)

Kunal P. Ganeshpure , University of Massachusetts Amherst, Amherst, USA
Sandip Kundu , University of Massachusetts Amherst, Amherst, USA
pp. 1-7

Silicon evaluation of longest path avoidance testing for small delay defects (PDF)

Ritesh Turakhia , Integrated Circuit Design & Test Laboratory, Portland, OR, USA
W. Robert Daasch , Integrated Circuit Design & Test Laboratory, Portland, OR, USA
Mark Ward , LSI Logic, Gresham, OR, USA
John Van Slyke , LSI Logic, Minneapolis, MN, USA
pp. 1-10

Advancements in at-speed array BIST: multiple improvements (PDF)

Kevin Gorman , IBM, Essex Junction, Vermont, USA
Michael Roberge , IBM, Essex Junction, Vermont, USA
Adrian Paparelli , IBM, Essex Junction, Vermont, USA
Gary Pomichter , IBM, Essex Junction, Vermont, USA
Stephen Sliva , IBM, Essex Junction, Vermont, USA
William Corbin , IBM, Essex Junction, Vermont, USA
pp. 1-10

A concurrent approach for testing address decoder faults in eFlash memories (PDF)

O. Ginez , Laboratoire d¿Informatique, de Robotique et de Microélectronique de Montpelier - LIRMM Université de Montpellier II/CNRS 161, rue Ada - 34392 Cedex 5, France
P. Girard , Laboratoire d¿Informatique, de Robotique et de Microélectronique de Montpelier - LIRMM Université de Montpellier II/CNRS 161, rue Ada - 34392 Cedex 5, France
C. Landrault , Laboratoire d¿Informatique, de Robotique et de Microélectronique de Montpelier - LIRMM Université de Montpellier II/CNRS 161, rue Ada - 34392 Cedex 5, France
S. Pravossoudovitch , Laboratoire d¿Informatique, de Robotique et de Microélectronique de Montpelier - LIRMM Université de Montpellier II/CNRS 161, rue Ada - 34392 Cedex 5, France
A. Virazel , Laboratoire d¿Informatique, de Robotique et de Microélectronique de Montpelier - LIRMM Université de Montpellier II/CNRS 161, rue Ada - 34392 Cedex 5, France
J.-M. Daga , ATMEL Rousset - Libraries and Design Tools Department Embedded Non-Volatile Memory Group - 13106 Cedex, France
pp. 1-10

Diagnosis for MRAM write disturbance fault (PDF)

Chin-Lung Su , Dept. of Electrical Engineering, National Tsing Hua University, Hsinchu, Taiwan, China
Chih-Wea Tsai , Dept. of Electrical Engineering, National Tsing Hua University, Hsinchu, Taiwan, China
Cheng-Wen Wu , Dept. of Electrical Engineering, National Tsing Hua University, Hsinchu, Taiwan, China
Ji-Jan Chen , SOC Technology Center, Industrial Technology Research Inst., Hsinchu Taiwan, China
Wen-Ching Wu , SOC Technology Center, Industrial Technology Research Inst., Hsinchu Taiwan, China
Chien-Chung Hung , Electronics Research and Service Org. Industrial Technology Research Inst., Hsinchu, Taiwan, China
Ming-Jer Kao , Electronics Research and Service Org. Industrial Technology Research Inst., Hsinchu, Taiwan, China
pp. 1-9

Data jitter measurement using a delta-time-to-voltage converter method (PDF)

Kiyotaka Ichiyama , Advantest Laboratories, Ltd., Sendai, Miyagi, Japan
Masahiro Ishida , Advantest Laboratories, Ltd., Sendai, Miyagi, Japan
Takahiro J. Yamaguchi , Advantest Laboratories, Ltd., Sendai, Miyagi, Japan
Mani Soma , Department of Electrical Engineering, University of Washington, Seattle, USA
pp. 1-7

New methods for receiver internal jitter measurement (PDF)

Mike P. Li , Waverest Corporation, 1735 Technology Dr., Suite 400, San Jose, Ca 951110, USA
Jinhua Chen , EMC Corporation, 176 South Street, Hopkinton, MA, USA
pp. 1-10

A selt-testing BOST for high-frequency PLLs, DLLs, and SerDes (PDF)

Stephen Sunter , Logic Vision (Canada), Inc. Ottawa, Canada
Aubin Roy , Logic Vision (Canada), Inc. Ottawa, Canada
pp. 1-8

Test-wrapper designs for the detection of signal-integrity faults on core-external interconnects of SoCs (PDF)

Qiang Xu , Computer Science and Engineering, The Chinese University of Hong Kong, Shatin, N.T., China
Yubin Zhang , Computer Science and Engineering, The Chinese University of Hong Kong, Shatin, N.T., China
Krishnendu Chakrabarty , Electrical and Computer Engineering, Duke University, Durham, NC 27708, USA
pp. 1-9

A heuristic for thermal-safe SoC test scheduling (PDF)

Zhiyuan He , Embedded Systems Laboratory (ESLAB), Linkping University, Sweden
Zebo Peng , Embedded Systems Laboratory (ESLAB), Linkping University, Sweden
Petru Eles , Embedded Systems Laboratory (ESLAB), Linkping University, Sweden
pp. 1-10

Redefining and testing interconnect faults in Mesh NoCs (PDF)

Erika Cota , Universidade Federal do Rio Grande do Sul, PPGC - Instituto de Informá, Po Box 15064, ZIP 91501-970, Porto Alegre, RS, Brazil
Fernanda Lima Kastensmidt , Universidade Federal do Rio Grande do Sul, PPGC - Instituto de Informá, Po Box 15064, ZIP 91501-970, Porto Alegre, RS, Brazil
Alexandre Amory , Universidade Federal do Rio Grande do Sul, PPGC - Instituto de Informá, Po Box 15064, ZIP 91501-970, Porto Alegre, RS, Brazil
Maico Cassel , Universidade Federal do Rio Grande do Sul, PPGC - Instituto de Informá, Po Box 15064, ZIP 91501-970, Porto Alegre, RS, Brazil
Marcelo Lubasweski , Universidade Federal do Rio Grande do Sul, PPGC - Instituto de Informá, Po Box 15064, ZIP 91501-970, Porto Alegre, RS, Brazil
Paulo Meirelles , Universidade Federal do Rio Grande do Sul, PPGC - Instituto de Informá, Po Box 15064, ZIP 91501-970, Porto Alegre, RS, Brazil
pp. 1-10

Fully X-tolerant combinational scan compression (PDF)

P. Wohl , Synopsys, Inc., USA
J.A. Waicukauski , Synopsys, Inc., USA
S. Ramnath , Synopsys, Inc., USA
pp. 1-10

X-canceling MISR — An X-tolerant methodology for compacting output responses with unknowns using a MISR (PDF)

Nur A. Touba , Computer Engineering Research Center, Department of Electrical and Computer Engineering University of Texas, Austin, 78712, USA
pp. 1-10

Using timing flexibility of automatic test equipment to complement X-tolerant test compression techniques (PDF)

Andreas Leininger , Infineon Technologies AG, Am Campeon 1-12 81726 Munich, Germany
Martin Fischer , Verigy Germany GmbH, Herrenberger Strasse 130 71034 Böblingen, Germany
Michael Braun , Verigy Germany GmbH, Herrenberger Strasse 130 71034 Böblingen, Germany
Michael Richter , University of Potsdam, August Bebel Stra?e 89 14482, Germany
Michael Goessel , University of Potsdam, August Bebel Stra?e 89 14482, Germany
pp. 1-9

Diagnose compound scan chain and system logic defects (PDF)

Yu Huang , Mentor Graphics Corp. 300 Nickerson Road, Marlborough, MA 01752, USA
Will Hsu , Taiwan Semiconductor Manufacturing Company, Li-Hsin Rd. 6, Hsinchu Science Park, Taiwan 300-77, China
Yuan-Shih Chen , Taiwan Semiconductor Manufacturing Company, Li-Hsin Rd. 6, Hsinchu Science Park, Taiwan 300-77, China
Wu-Tung Cheng , Mentor Graphics Corp. 8005 SW Boeckman Rd, Wilsonville, OR 97068, USA
Ruifeng Guo , Mentor Graphics Corp. 8005 SW Boeckman Rd, Wilsonville, OR 97068, USA
Albert Man , Advanced Micro Devices Inc., 1 Commerce Valley Drive East, Markham, Ontario, Canada L3T 7X6, USA
pp. 1-10

A complete test set to diagnose scan chain failures (PDF)

Ruifeng Guo , Mentor Graphics Corp. Wilsonville, OR 97070, USA
Yu Huang , Mentor Graphics Corp. Wilsonville, OR 97070, USA
Wu-Tung Cheng , Mentor Graphics Corp. Wilsonville, OR 97070, USA
pp. 1-10

Interconnect open defect diagnosis with minimal physical information (PDF)

Chen Liu , ECE Dept., University of Iowa City, 52242, USA
Wei Zou , Mentor Graphics Corporation, 8005 SW Boeckman Road, Wilsonville, OR 97070, U.S.A
Sudhakar M. Reddy , ECE Dept., University of Iowa City, 52242, USA
Wu-Tung Cheng , Mentor Graphics Corporation, 8005 SW Boeckman Road, Wilsonville, OR 97070, U.S.A
Manish Sharma , Mentor Graphics Corporation, 8005 SW Boeckman Road, Wilsonville, OR 97070, U.S.A
Huaxing Tang , Mentor Graphics Corporation, 8005 SW Boeckman Road, Wilsonville, OR 97070, U.S.A
pp. 1-10

Multi-GHz loopback testing using MEMs switches and SiGe logic (PDF)

D.C. Keezer , Georgia Institute of Technology, Atlanta, USA
D. Minier , IBM, Bromont, Canada, USA
P. Ducharme , IBM, Bromont, Canada, USA
D. Viens , IBM, Bromont, Canada, USA
G. Flynn , TeraVicta, Austin, Texas, USA
J. S. McKillop , TeraVicta, Austin, Texas, USA
pp. 1-10

Critical roles of RF and microwave electromagnetic field solver simulators in multi-gigabit high-speed digital applications (PDF)

Minh Quach , Avago Technologies ASIC Product Division Fort Collins, Colorado, USA
Mark Hinton , Avago Technologies ASIC Product Division Fort Collins, Colorado, USA
Regee Petaja , Avago Technologies ASIC Product Division Fort Collins, Colorado, USA
pp. 1-9

Testing of Vega2, a chip multi-processor with spare processors. (PDF)

Samy Makar , Azul Systems, 1600 Plymouth Ave, Mountain View, CA 94043, USA
Tony Altinis , Azul Systems, 1600 Plymouth Ave, Mountain View, CA 94043, USA
Niteen Patkar , Azul Systems, 1600 Plymouth Ave, Mountain View, CA 94043, USA
Janet Wu , Azul Systems, 1600 Plymouth Ave, Mountain View, CA 94043, USA
pp. 1-10

The design-for-testability features of a general purpose microprocessor (PDF)

Da Wang , Key Laboratory of Computer System and Architecture, Institute of Computing Technology, Chinese Academy of Sciences, Beijing, China
Xiaoxin Fan , Key Laboratory of Computer System and Architecture, Institute of Computing Technology, Chinese Academy of Sciences, Beijing, China
Xiang Fu , Key Laboratory of Computer System and Architecture, Institute of Computing Technology, Chinese Academy of Sciences, Beijing, China
Hui Liu , Key Laboratory of Computer System and Architecture, Institute of Computing Technology, Chinese Academy of Sciences, Beijing, China
Ke Wen , Key Laboratory of Computer System and Architecture, Institute of Computing Technology, Chinese Academy of Sciences, Beijing, China
Rui Li , STMicroelectronics (Shanghai) Co., Ltd., China
Huawei Li , Key Laboratory of Computer System and Architecture, Institute of Computing Technology, Chinese Academy of Sciences, Beijing, China
Yu Hu , Key Laboratory of Computer System and Architecture, Institute of Computing Technology, Chinese Academy of Sciences, Beijing, China
Xiaowei Li , Key Laboratory of Computer System and Architecture, Institute of Computing Technology, Chinese Academy of Sciences, Beijing, China
pp. 1-9

Design for test features of the ARM clock control macro (PDF)

Frank Frederick , ARM, Austin, Texas USA
Teresa McLaurin , ARM, Austin, Texas USA
pp. 1-8

Analyzing the risk of timing modeling based on path delay tests. (PDF)

Pouria Bastani , Department of ECE, UC-Santa Barbara, USA
Benjamin N. Lee , Department of ECE, UC-Santa Barbara, USA
Li-C. Wang , Department of ECE, UC-Santa Barbara, USA
Savithri Sundareswaran , Freescale Semiconductor, Inc., USA
Magdy S. Abadir , Freescale Semiconductor, Inc., USA
pp. 1-10

Mining-guided state justification with partitioned navigation tracks (PDF)

Ankur Parikh , Department of Electrical & Computer Engineering, Virginia Tech, Blacksburg, USA
Weixin Wu , Department of Electrical & Computer Engineering, Virginia Tech, Blacksburg, USA
Michael S. Hsiao , Department of Electrical & Computer Engineering, Virginia Tech, Blacksburg, USA
pp. 1-10

An efficient SAT-based path delay fault ATPG with an unified sensitization model (PDF)

Shun-Yen Lu , Department of Electrical Engineering, National Tsing Hua University, Hsinchu, Taiwan 30013, China
Ming-Ting Hsieh , Department of Electrical Engineering, National Tsing Hua University, Hsinchu, Taiwan 30013, China
Jing-Jia Liou , Department of Electrical Engineering, National Tsing Hua University, Hsinchu, Taiwan 30013, China
pp. 1-7

Characterization of NBTI induced temporal performance degradation in nano-scale SRAM array using IDDQ (PDF)

Kunhyuk Kang , Purdue University,West Lafayette, Indiana, USA
Muhammad Ashraful Alam , Purdue University,West Lafayette, Indiana, USA
Kaushik Roy , Purdue University,West Lafayette, Indiana, USA
pp. 1-10

Separating temperature effects from ring-oscillator readings to measure true IR-drop on a chip (PDF)

Zahi Abuhamdeh , TranSwitch Corporation, 34 Crosby Drive, Bedford MA, 01730, USA
Vincent D'Alassandro , TranSwitch Corporation, 34 Crosby Drive, Bedford MA, 01730, USA
Richard Pico , TranSwitch Corporation, 34 Crosby Drive, Bedford MA, 01730, USA
Dale Montrone , TranSwitch Corporation, 34 Crosby Drive, Bedford MA, 01730, USA
Alfred Crouch , Inovys Corporation, 1715 Warwick Way, Cedar Park, TX 78613, USA
Andrew Tracy , TranSwitch Corporation, 34 Crosby Drive, Bedford MA, 01730, USA
pp. 1-10

Gate delay ratio model for unified path delay analysis (PDF)

Yukio Okuda , Sony Corporation, Atsugi Japan
pp. 1-10

Rapid UHF RFID silicon debug and production testing (PDF)

Udaya Shankar Natarajan , Intel Corporation, 1900 Prairie City Road, Folsom CA 95630, USA
Hemalatha Shanmugasundaram , Intel Corporation, 1900 Prairie City Road, Folsom CA 95630, USA
Prachi Deshpande , Intel Corporation, 1900 Prairie City Road, Folsom CA 95630, USA
Chin Soon Wah , Intel Corporation, 1900 Prairie City Road, Folsom CA 95630, USA
pp. 1-10

A high accuracy high throughput jitter test solution on ATE for 3GBPS and 6gbps serial-ata (PDF)

Yongquan Fan , LSI Corporation, 1110 American Parkway NE, Allentown, Pennsylvania 18109, USA
Yi Cai , LSI Corporation, 1110 American Parkway NE, Allentown, Pennsylvania 18109, USA
Zeljko Zilic , Department of ECE, McGill University, USA
pp. 1-10

High throughput non-contact SiP testing (PDF)

M. Reja , Scanimetrics Inc. RTF, 8308 - 114 Street, Edmonton, Alberta, T6G 2E1, Canada
B. Moore , Scanimetrics Inc. RTF, 8308 - 114 Street, Edmonton, Alberta, T6G 2E1, Canada
P. Cauvet , NXP Semiconductors, 2 Esplanade Anton Philips B.P. 20000 14906 Caen Cedex 9, France
H. Fleury , NXP Semiconductors, 2 Esplanade Anton Philips B.P. 20000 14906 Caen Cedex 9, France
M. Paulson , Scanimetrics Inc. RTF, 8308 - 114 Street, Edmonton, Alberta, T6G 2E1, Canada
C. Sellathamby , Scanimetrics Inc. RTF, 8308 - 114 Street, Edmonton, Alberta, T6G 2E1, Canada
L. Fu , Scanimetrics Inc. RTF, 8308 - 114 Street, Edmonton, Alberta, T6G 2E1, Canada
B. Bai , Scanimetrics Inc. RTF, 8308 - 114 Street, Edmonton, Alberta, T6G 2E1, Canada
E. Reid , Scanimetrics Inc. RTF, 8308 - 114 Street, Edmonton, Alberta, T6G 2E1, Canada
I. Filanovsky , Department of Electrical and Computer Engineering, University of Alberta, Edmonton, T6G 2V4, Canada
S. Slupsky , Scanimetrics Inc. RTF, 8308 - 114 Street, Edmonton, Alberta, T6G 2E1, Canada
pp. 1-10

A stochastic pattern generation and optimization framework for variation-tolerant, power-safe scan test (PDF)

V.R. Devanathan , Texas Instruments India Pvt. Ltd., Bangalore - 560 093, India
C.P. Ravikumar , Texas Instruments India Pvt. Ltd., Bangalore - 560 093, India
V. Kamakoti , Department of Computer Science and Engg., Indian Institute of Technology, Madras - 600 036, India
pp. 1-10

Efficient power droop aware delay fault testing (PDF)

Bin Li , Department of Electrical and Computer Engineering, Virginia Tech, USA
Lei Fang , Department of Electrical and Computer Engineering, Virginia Tech, USA
Michael S. Hsiao , Department of Electrical and Computer Engineering, Virginia Tech, USA
pp. 1-10

PMScan : A power-managed scan for simultaneous reduction of dynamic and leakage power during scan test (PDF)

V.R. Devanathan , Texas Instruments India Pvt. Ltd., Bangalore, - 560 093, India
C.P. Ravikumar , Texas Instruments India Pvt. Ltd., Bangalore, - 560 093, India
Rajat Mehrotra , Texas Instruments India Pvt. Ltd., Bangalore, - 560 093, India
V. Kamakoti , Department of Computer Science and Engg., Indian Institute of Technology, Madras - 600 036, India
pp. 1-9

Implementing bead probe technology for in-circuit test: A case study (PDF)

Mike Farrell , Agilent Technologies, Loveland, Colorado, USA
Glen Leinbach , Caber Contacts, LLC, Fort Collins, Colorado, USA
pp. 1-8

A bead probe CAD strategy for in-circuit test (PDF)

Kenneth P. Parker , Agilent Technologies, Loveland, CO, USA
Don DeMille , DeMille Research Inc., Lake Forest, CA, USA
pp. 1-8

Impact of Quad Flat No Lead package (QFN) on automated X-ray inspection (AXI) (PDF)

Chwee Liong , Test Development Engineering (Malaysia), Intel Kulim, Malaysia
Tee , Test Development Engineering (Malaysia), Intel Kulim, Malaysia
Andy Pascual , Measurement Systems Division, Agilent Technologies Singapore (Sales), Singapore
pp. 1-10

Delay defect diagnosis using segment network faults (PDF)

Osei Poku , Laboratory for Integrated Systems Test, Department of Electrical and Computer Engineering, Carnegie Mellon University, Pittsburgh PA 15213, USA
R. D. Blanton , Laboratory for Integrated Systems Test, Department of Electrical and Computer Engineering, Carnegie Mellon University, Pittsburgh PA 15213, USA
pp. 1-10

Testing for systematic defects based on DFM guidelines (PDF)

Dongok Kim , Purdue University, West Lafayette, IN, USA
M. Enamul Amyeen , Intel Corporation, Hillsboro, OR, USA
Srikanth Venkataraman , Intel Corporation, Hillsboro, OR, USA
Irith Pomeranz , Purdue University, West Lafayette, IN, USA
Swagato Basumallick , Intel Corporation, Hillsboro, OR, USA
Berni Landau , Intel Corporation, Hillsboro, OR, USA
pp. 1-10

Faster defect localization in nanometer technology based on defective cell diagnosis (PDF)

Manish Sharma , Mentor Graphics Corporation, 8005 SW Boeckman Rd., Wilsonville, OR 97070, USA
Wu-Tung Cheng , Mentor Graphics Corporation, 8005 SW Boeckman Rd., Wilsonville, OR 97070, USA
Ting-Pu Tai , Mentor Graphics Corporation, 8005 SW Boeckman Rd., Wilsonville, OR 97070, USA
Y.S. Cheng , Taiwan Semiconductor Manufacturing Company, 8, Li-Hsin Rd. 6, Hsinchu Science Park, Taiwan 300-77, China
Will Hsu , Taiwan Semiconductor Manufacturing Company, 8, Li-Hsin Rd. 6, Hsinchu Science Park, Taiwan 300-77, China
Chen Liu , Department of ECE, University of Iowa, 52242, USA
Sudhakar M. Reddy , Department of ECE, University of Iowa, 52242, USA
Albert Mann , AMD, Inc., 1CV Commerce Valley Drive E., Markham, Ont, L3T 7N6, Canada
pp. 1-10

Real-time signal processing - a new PLL test approach (PDF)

Hideo Okawara , Verigy (Japan) K.K. Tokyo, Japan
pp. 1-9

A methodology for systematic built-in self-test of phase-locked loops targeting at parametric failures (PDF)

Guo Yu , Department of ECE, Texas A&M University, College Station, 77843, U.S.A.
Peng Li , Department of ECE, Texas A&M University, College Station, 77843, U.S.A.
pp. 1-10

An FFT-based jitter separation method for high-frequency jitter testing with a 10x reduction in test time (PDF)

Takahiro J. Yamaguchi , Advantest Laboratories, Ltd., Sendai, Miyagi, Japan
Masahiro Ishida , Advantest Laboratories, Ltd., Sendai, Miyagi, Japan
Harry X. Hou , Advantest America, Inc., Santa Clara, CA, USA
Dave Armstrong , Advantest America, Inc., Santa Clara, CA, USA
Koji Takayama , Sony LSI Design Inc., Sapporo, Hokkaido, Japan
Mani Soma , Department of Electrical Engineering, University of Washington, Seattle, USA
pp. 1-8

Achieving high transition delay fault coverage with partial DTSFF scan chains (PDF)

Gefu Xu , Auburn University, AL, USA
Adit D. Singh , Auburn University, AL, USA
pp. 1-9

Fundamentals of timing information for test: How simple can we get? (PDF)

Rohit Kapur , Sypnosys Inc., Mountain View, CA 9404, USA
Jindrich Zejda , Sypnosys Inc., Mountain View, CA 9404, USA
T. W. Williams , Sypnosys Inc., Mountain View, CA 9404, USA
pp. 1-7

Automated handling of programmable on-product clock generation (OPCG) circuitry for delay test vector generation (PDF)

Anis Uzzaman , Cadence Design Systems, Inc., Endicott, New York 13760, USA
Bibo Li , Cadence Design Systems, Inc., Endicott, New York 13760, USA
Tom Snethen , Cadence Design Systems, Inc., Endicott, New York 13760, USA
Brion Keller , Cadence Design Systems, Inc., Endicott, New York 13760, USA
Gary Grise , International Business Machines, Inc., Burlington, Vermont, USA
pp. 1-10

A low cost test data compression technique for high n-detection fault coverage (PDF)

Seongmoon Wang , NEC Labs. America, Princeton, NJ, USA
Wenlong Wei , NEC Labs. America, Princeton, NJ, USA
Srimat T. Chakradhar , NEC Labs. America, Princeton, NJ, USA
Zhanglei Wang , Cisco Systems, USA
pp. 1-10

On using lossless compression of debug data in embedded logic analysis (PDF)

Ehab Anis , Department of Electrical and Computer Engineering, McMaster University, Hamilton, ON L8S 4K1, Canada
Nicola Nicolici , Department of Electrical and Computer Engineering, McMaster University, Hamilton, ON L8S 4K1, Canada
pp. 1-10

Functional testing of digital microfluidic biochips (PDF)

Tao Xu , Department of Electrical and Computer Engineering, Duke University, Durham, NC 27708, USA
Krishnendu Chakrabarty , Department of Electrical and Computer Engineering, Duke University, Durham, NC 27708, USA
pp. 1-10

Enhancing signal controllability in functional test-benches through automatic constraint extraction (PDF)

Onur Guzey , Department of ECE, UC-Santa Barbara, USA
Li-C. Wang , Department of ECE, UC-Santa Barbara, USA
Jayanta Bhadra , Freescale Semiconductor, Inc., USA
pp. 1-10

The new ATE: Protocol aware (PDF)

Andrew C. Evans , Broadcom Corporation Irvine, California, USA
pp. 1-10

A matched expansion MEMS probe card with low CTE LTCC substrate (PDF)

Seong-Hun Choe , Department of Nanomechanics, Graduate School of Engineering, Tohoku University, Sendai, Miyagi 980-8579, Japan
Shuji Tanaka , Department of Nanomechanics, Graduate School of Engineering, Tohoku University, Sendai, Miyagi 980-8579, Japan
Masayoshi Esashi , Department of Nanomechanics, Graduate School of Engineering, Tohoku University, Sendai, Miyagi 980-8579, Japan
pp. 1-6

Management of common-mode currents in semiconductor ATE (PDF)

William J. Bowhers , Merrimack College, North Andover, MA, USA
pp. 1-9

SPARTAN: a spectral and information theoretic approach to partial-scan (PDF)

Omar I. Khan , Dept. of ECE and CAIP Research Center, Rutgers University, 96 Frelinghuysen Road, Piscataway, NJ 08854-8088, USA
Michael L. Bushnell , Dept. of ECE and CAIP Research Center, Rutgers University, 96 Frelinghuysen Road, Piscataway, NJ 08854-8088, USA
Suresh K. Devanathan , Dept. of ECE and CAIP Research Center, Rutgers University, 96 Frelinghuysen Road, Piscataway, NJ 08854-8088, USA
Vishwani D. Agrawal , Dept. of ECE, Auburn University, AL 36849, USA
pp. 1-10

A scanisland based design enabling prebond testability in die-stacked microprocessors (PDF)

Dean L. Lewis , School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, 30332, USA
Hsien Hsin S. Lee , School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, 30332, USA
pp. 1-8

A generic and reconfigurable test paradigm using Low-cost integrated Poly-Si TFTs (PDF)

Jing Li , Electrical and Computer Engineering, Purdue University, West Lafayette, IN 47906, USA
Swaroop Ghosh , Electrical and Computer Engineering, Purdue University, West Lafayette, IN 47906, USA
Kaushik Roy , Electrical and Computer Engineering, Purdue University, West Lafayette, IN 47906, USA
pp. 1-10

Co-development of test electronics and PCI Express interface for a multi-Gbps optical switching network (PDF)

C.E. Gray , Georgia Institute of Technology, Atlanta, USA
O. Liboiron- Ladouceur , Columbia University, New York City, USA
D.C. Keezer , Georgia Institute of Technology, Atlanta, USA
K. Bergman , Columbia University, New York City, USA
pp. 1-9

Finding power/ground defects on connectors — a new approach (PDF)

Kenneth P. Parker , Agilent Technologies, Loveland, Colorado, USA
Stephen Hird , Agilent Technologies, Loveland, Colorado, USA
pp. 1-7

Statistical analysis and optimization of parametric delay test (PDF)

Sean H. Wu , Department of ECE, UC-Santa Barbara, USA
Benjamin N. Lee , Department of ECE, UC-Santa Barbara, USA
Li-C. Wang , Department of ECE, UC-Santa Barbara, USA
Magdy S. Abadir , Freescale Semiconductor, Inc., USA
pp. 1-10

Verification and debugging of IDDQ test of low power chips (PDF)

M. Laisne , Qualcomm Inc, San Diego, CA, USA
T. Nguyen , Qualcomm Inc, San Diego, CA, USA
S. Zuo , Qualcomm Inc, San Diego, CA, USA
X. Pan , Qualcomm Inc, San Diego, CA, USA
H. Cui , Qualcomm Inc, San Diego, CA, USA
C. Bai , Qualcomm Inc, San Diego, CA, USA
A. Street , Qualcomm Inc, San Diego, CA, USA
M. Parley , Qualcomm Inc, San Diego, CA, USA
N. Agrawal , Qualcomm Inc, San Diego, CA, USA
K. Sundararaman , Qualcomm Inc, San Diego, CA, USA
pp. 1-7

Low cost automatic mixed-signal board test using IEEE 1149.4 (PDF)

Srividya Sundar , University of Alabama, Tuscaloosa, USA
Bruce C. Kim , University of Alabama, Tuscaloosa, USA
Toby Byrd , Automated Circuit Design, USA
Felipe Toledo , Automated Circuit Design, USA
Sudhir Wokhlu , Texas Instruments Inc., USA
Erika Beskar , Texas Instruments Inc., USA
Raul Rousselin , Texas Instruments Inc., USA
David Cotton , Texas Instruments Inc., USA
Gary Kendall , Texas Instruments Inc., USA
pp. 1-9

Efficient simulation of parametric faults for multi-stage analog circuits (PDF)

Fang Liu , Department of Electrical & Computer Engineering, Duke University, USA
Sule Ozev , Department of Electrical & Computer Engineering, Duke University, USA
pp. 1-9

Using built-in sensors to cope with long duration transient faults in future technologies (PDF)

C. A. Lisboa , Instituto de Informática, PPGC, Universidade Federal do Rio Grande do Sul, Brazil
F. L. Kastensmidt , Instituto de Informática, PPGC, Universidade Federal do Rio Grande do Sul, Brazil
E. Henes Neto , Engenharia de Sistemas Digitais, Universidade Estadual do Rio Grande do Sul, Brazil
G. Wirht , Departamento de Engenharia Elétrica, PPGEE, Universidade Federal do Rio Grande do Sul, Brazil
L. Carro , Instituto de Informática, PPGC, Universidade Federal do Rio Grande do Sul, Brazil
pp. 1-10

A novel scheme to reduce power supply noise for high-quality at-speed scan testing (PDF)

Xiaoqing Wen , Kyushu Institute of Technology, Iizuka 820-8502, Japan
Kohei Miyase , Kyushu Institute of Technology, Iizuka 820-8502, Japan
Seiji Kajihara , Kyushu Institute of Technology, Iizuka 820-8502, Japan
Tatsuya Suzuki , Kyushu Institute of Technology, Iizuka 820-8502, Japan
Yuta Yamato , Kyushu Institute of Technology, Iizuka 820-8502, Japan
Patrick Girard , LIRMM, 161 rue Ada, 34392 Montpellier cedex 05, France
Yuji Ohsumi , Hibikino R&D Center, DNP Co. Ltd., Kitakyushu 808-0135, Japan
Laung-Terng Wang , SynTest Technologies, Inc., 505 S. Pastoria Ave., Sunnyvale, CA 94086, USA
pp. 1-10

Pattern-directed circuit virtual partitioning for test power reduction (PDF)

Qiang Xu , Dept. of Computer Science & Engineering, The Chinese University of Hong Kong, Shatin, N.T., China
Dianwei Hu , Dept. of Computer Science & Technology, Tsinghua University, Beijing 100084, China
Dong Xiang , School of Software, Tsinghua University, Beijing 100084, China
pp. 1-10

California scan architecture for high quality and low power testing (PDF)

Kyoung Youn Cho , Center for Reliable Computing (CRC), Department of Electrical Engineering, Stanford University, CA, USA
Subhasish Mitra , Center for Reliable Computing (CRC), Department of Electrical Engineering, Stanford University, CA, USA
Edward J. McCluskey , Center for Reliable Computing (CRC), Department of Electrical Engineering, Stanford University, CA, USA
pp. 1-10

Estimating stuck fault coverage in sequential logic using state traversal and entropy analysis (PDF)

Soumitra Bose , Design Technology, Intel Corp., Folsom, CA 95630, USA
Vishwani D. Agrawal , Dept. of ECE, Auburn University, Auburn, AL 36849, USA
pp. 1-10

Fast and effective fault simulation for path delay faults based on selected testable paths (PDF)

Dong Xiang , School of Software, Tsinghua University, Beijing 100084, China
Yang Zhao , Dept. of Comp. Sci., Tsinghua University, Beijing 100084, China
Kaiwei Li , Dept. of Comp. Sci., Tsinghua University, Beijing 100084, China
Hideo Fujiwara , Graduate Sch. of Inform. Sci., Nara Inst. of Sci. and Techn., Ikoma, Nara 630-0101, Japan
pp. 1-10

Delay fault simulation with bounded gate delay mode (PDF)

Soumitra Bose , Design Technology, Intel Corp. Folsom, CA 95630, USA
Hillary Grimes , Dept. of ECE, Auburn University, AL 36849, USA
Vishwani D. Agrawal , Dept. of ECE, Auburn University, AL 36849, USA
pp. 1-10

ERTG: A test generator for error-rate testing (PDF)

Shideh Shahidi , Department of EE Systems, University of Southern California, Los Angeles, 90089, USA
Sandeep K. Gupta , Department of EE Systems, University of Southern California, Los Angeles, 90089, USA
pp. 1-10

ACCE: Automatic correction of control-flow errors (PDF)

Ramtilak Vemu , Computer Engineering Research Center, University of Texas at Austin, USA
Sankar Gurumurthy , Computer Engineering Research Center, University of Texas at Austin, USA
Jacob A. Abraham , Computer Engineering Research Center, University of Texas at Austin, USA
pp. 1-10

Modeling facet roughening errors in self-assembly by snake tile sets (PDF)

X. Ma , Dept of Electrical and Computer Engineering, Northeastern University, Boston, MA 02115, USA
J. Huang , Dept of Electrical and Computer Engineering, Northeastern University, Boston, MA 02115, USA
F. Lombardi , Dept of Electrical and Computer Engineering, Northeastern University, Boston, MA 02115, USA
pp. 1-10

Low cost characterization of RF transceivers through IQ data analysis (PDF)

Erkan Acar , Duke University, Durham, NC 27708, USA
Sule Ozev , Duke University, Durham, NC 27708, USA
pp. 1-10

Test yield estimation for analog/RF circuits over multiple correlated measurements (PDF)

Fang Liu , Department of Electrical & Computer Engineering, Duke University, USA
Erkan Acar , Department of Electrical & Computer Engineering, Duke University, USA
Sule Ozev , Department of Electrical & Computer Engineering, Duke University, USA
pp. 1-10

Dependable clock distribution for crosstalk aware design (PDF)

Yukiya Miura , Faculty of System Design, Tokyo Metropolitan University, Japan
pp. 1-9

Novel compensation scheme for local clocks of high performance microprocessors (PDF)

C. Metra , DEIS ¿ Univ. of Bologna, Italy
M. Omana , DEIS ¿ Univ. of Bologna, Italy
TM Mak , Intel Corporation, Santa Clara, CA, USA
S. Tam , Intel Corporation, Santa Clara, CA, USA
pp. 1-9

A methodology for detecting performance faults in microprocessors via performance monitoring hardware (PDF)

M. Hatzimihail , Department of Informatics, University of Piraeus, Greece
M. Psarakis , Department of Informatics, University of Piraeus, Greece
D. Gizopoulos , Department of Informatics, University of Piraeus, Greece
A. Paschalis , Department of Informatics & Telecommunications, University of Athens, Greece
pp. 1-10

On the saturation of n-detection test sets with increased n (PDF)

Irith Pomeranz , School of Electrical & Computer Eng., Purdue University, W. Lafayette, IN 47907, USA
Sudhakar M. Reddy , Electrical & Computer Eng. Dept., University of Iowa, 52242, USA
pp. 1-10

Achieving serendipitous N-detect mark-offs in Multi-Capture-Clock scan patterns (PDF)

Gaurav Bhargava , Qualcomm San Diego, CA, USA
Dale Meehl , Cadence Design Systems, Inc. Endicott, New York, USA
James Sage , Cadence Design Systems, Inc. Endicott, New York, USA
pp. 1-7

Embedded multi-detect ATPG and Its Effect on the Detection of Unmodeled Defects (PDF)

Jeroen Geuzebroek , NXP Semiconductors, Corporate I&T / Research, High Tech Campus 37, 5656AE Eindhoven, The Netherlands
Erik Jan Marinissen , NXP Semiconductors, Corporate I&T / DTF, High Tech Campus 37, 5656AE Eindhoven, The Netherlands
Ananta Majhi , NXP Semiconductors, Corporate I&T / DTF, High Tech Campus 37, 5656AE Eindhoven, The Netherlands
Andreas Glowatz , NXP Semiconductors, Corporate I&T / DTF, Georg-Heyken-Stra?e 1, D-21147 Hamburg, Germany
Friedrich Hapke , NXP Semiconductors, Corporate I&T / DTF, Georg-Heyken-Stra?e 1, D-21147 Hamburg, Germany
pp. 1-10

A comparative study of continuous sampling plans for functional board testing (PDF)

Jukka Antila , Nokia Siemens Networks, Finland
Timo Karhu , Nokia Siemens Networks, Finland
pp. 1-7

Enhanced testing of clock faults (PDF)

Teresa L. McLaurin , ARM Inc., 1250 S. Capital of TX Hwy, Bldg 3, Ste 560, Austin, TX 78746, USA
Richard Slobodnik , ARM Inc., 1250 S. Capital of TX Hwy, Bldg 3, Ste 560, Austin, TX 78746, USA
Kun-Han Tsai , Mentor Graphics Corporation, 8005 S.W. Boeckman Road, OR 97070, USA
Ana Keim , Mentor Graphics Corporation, 8005 S.W. Boeckman Road, OR 97070, USA
pp. 1-9

SiP-test: Predicting delivery quality (PDF)

Alex Biewenga , NXP Semiconductors, Eindhoven, The Netherlands
Frans de Jong , NXP Semiconductors, Eindhoven, The Netherlands
pp. 1-10

A stereo audio Σ∑ ADC architecture with embedded SNDR self-test (PDF)

Luis Rolindez , STMicroelectronics, 850 rue Jean Monnet, Crolles, France
Jean-Louis Carbonero , STMicroelectronics, 850 rue Jean Monnet, Crolles, France
Dimitri Goguet , STMicroelectronics, 850 rue Jean Monnet, Crolles, France
Salvador Mir , TIMA Laboratory, 46 Avenue Flix Viallet, Grenoble, France
Nabil Chouba , STMicroelectronics, 2083 La Gazelle Ariana, Tunis, Tunisia
pp. 1-10

Sigma-delta ADC characterization using noise transfer function pole-zero tracking (PDF)

Hochul Kim , Texas Instruments Inc. Dallas, USA
Kye-shin Lee , Texas Instruments Inc. Dallas, USA
pp. 1-9

A fully digital-compatible BIST strategy for ADC linearity testing (PDF)

Hanqing Xing , Department of Electrical and Computer Engineering, Iowa State University, Ames, 50011, USA
Hanjun Jiang , Texas Instruments Inc., Dallas, 75243, USA
Degang Chen , Department of Electrical and Computer Engineering, Iowa State University, Ames, 50011, USA
Randall Geiger , Department of Electrical and Computer Engineering, Iowa State University, Ames, 50011, USA
pp. 1-10

IJTAG: The path to organized instrument connectivity (PDF)

Alfred L. Crouch , Inovys Corporation, Austin, TX, USA
pp. 1-10

JTAG system test in a MicroTCA world (PDF)

Bradford G. Van Treuren , Alcatel-Lucent, Murray Hill, New Jersey, USA
Adam Ley , ASSET InterTech, Inc., Richardson, Texas, USA
pp. 1-10

Protocol requirements in an SJTAG/IJTAG environment (PDF)

Gunnar Carlsson , PDU Base Station, Ericsson AB, Sweden
Johan Holmqvist , Department of Computer Science, Linkping University, Sweden
Erik Larsson , Department of Computer Science, Linkping University, Sweden
pp. 1-9

Power dissipation, variations and nanoscale CMOS design: Test challenges and self-calibration/self-repair solutions (PDF)

Swarup Bhunia , Dept of EECS, Case Western Reserve University, USA
Kaushik Roy , Dept of ECE, Purdue University, USA
pp. 1-10

Power-aware test: Challenges and solutions (PDF)

Srivaths Ravi , Texas Instruments India Pvt. Ltd., Bangalore - 560 093, India
pp. 1-10

A practical approach to comprehensive system test & debug using boundary scan based test architecture (PDF)

Tapan J. Chakraborty , ALCATEL-LUCENT, 67 Whippany Road, Whippany, NJ - 07981, USA
Chen-Huan Chiang , ALCATEL-LUCENT, 67 Whippany Road, Whippany, NJ - 07981, USA
Bradford G. Van Treuren , ALCATEL-LUCENT, 600 Mountain Avenue, Murray Hill, NJ - 07974, USA
pp. 1-10

Design-for-reliability: A soft error case study (PDF)

Ming Zhang , Intel Corporation, Folsom, CA, USA
pp. 1

Circuit failure prediction to overcome scaled CMOS reliability challenges (PDF)

Subhasish Mitra , Departments of Electrical Engineering and Computer Science, Stanford University, CA, USA
Mridul Agarwal , Departments of Electrical Engineering and Computer Science, Stanford University, CA, USA
pp. 1-3

At-speed scan tests: Reality or fantasy? (PDF)

Dhiraj Goswami , Synopsy Inc., 2025 NW Cornelias Pass Rd., Hillsboro, OR 97124, USA
Nilanjan Mukherjee , Mentor Graphics Corp., 8005 SW Boeckman Rd., Wilsonville, OR 97007, USA
pp. 1

At-speed structural test: Getting more real every day (PDF)

Kenneth M. Butler , Texas Instruments, Inc. Dallas, USA
pp. 1

At-speed scan tests are a reality (and a necessity) (PDF)

Grady Giles , Advanced Micro Devices, Inc. Austin, TX, USA
pp. 1

At-speed scan tests: Reality or fantasy? (PDF)

Srinivas Patil , Validation and Test Solutions, Intel Corporation, Austin, Texas, USA
pp. 1

At-speed scan tests: Reality or fantasy? (PDF)

Rajesh Raina , Freescale Semiconductor, 7700 W. Parmer Ln, Austin, TX 78729, USA
pp. 1-2

Boundary-scan: Built to last? Panel synopsis (PDF)

Bill Eklow , Cisco Systems, Inc., San Jose CA, USA
pp. 1

JTAG: Is it still up to snuff? (PDF)

Alfred L. Crouch , Inovys Corporation, Austin, TX, USA
pp. 1

Boundary-scan: Built to last? panel position (PDF)

Jay Nejedlo , Intel, Hillsboro, OR, USA
pp. 1-2

Is IEEE Std 1149.1 running out of gas? No way! (PDF)

Kenneth P. Parker , Agilent Technologies, Loveland, CO, USA
pp. 1

How can the results of silicon debug justify the investment in design-for- debug infrastructure? (PDF)

Srikanth Venkataraman , Intel Corporation, 2501 N.W. 229th Street, Hillsboro, OR 97124, USA
pp. 1

COT flow imposes added requirements for debug (PDF)

Zahi Abuhamdeh , TranSwitch Corporation, Bedford MA 01730, USA
pp. 1

How much insurance can you afford? (PDF)

Bruce Cory , NVIDIA, 2701 San Tomas Expressway, Santa Clara, CA 95050, USA
pp. 1

How can the results of silicon debug justify the investment in design-for- debug infrastructure? (PDF)

Bob Gottlieb , Intel Corporation, 2200 Mission College Blvd, Santa Clara, CA 95052, USA
pp. 1

Design-for-debug to address next-generation soc debug concerns (PDF)

Bart Vermeulen , NXP Semiconductors / Corporate Innovation and Technology / Research, High Tech Campus 37,5656 AE Eindhoven, The Netherlands
pp. 1

Does test have a greater role to play in the DFM process? (PDF)

Srikanth Venkataraman , Intel Corporation Hillsboro, OR 97124, USA
pp. 1

Well-targeted design-for-manufacturability[DFM] through test (PDF)

Anne Gattiker , IBM Austin Research Lab Austin, TX, USA
pp. 1

Does test have a greater role to play in the DFM process? (PDF)

Sandip Kundu , Department of Electrical and Computer Engineering University of Massachusetts, Amherst 01002, USA
pp. 1

The essential role of test in DFM (PDF)

D. M. H. Walker , Dept. of Computer Science, Texas A&M University College Station 77843-3112, USA
pp. 1

Position statement (PDF)

Robert Madge , LSI Corporation, USA
pp. 1

ITC 2007 panel session the new ATE: Protocol aware (PDF)

Andrew C. Evans , Broadcom Corporation Irvine, California, USA
pp. 1

Protocol aware test .. It has a role, but where? And how? (PDF)

Burlison , Inovys Corporation, USA
Crouch , Inovys Corporation, USA
Ritchie , Inovys Corporation, USA
pp. 1

Panel synopsis: Where is car IC testing going? (PDF)

Yukio Okuda , Sony Corp., ITC-Asia Subcommittee Atsugi Japan
pp. 1

SiP testing strategy for automobile LSI (PDF)

Hideyuki Aoki , Renesas Technology Corp. Tokyo, Japan
pp. 1

Where is car IC testing going? (PDF)

Steve Comen , Texas Instruments, Inc. Dallas, USA
pp. 1

Car IC test changing but the same quality goal (PDF)

Gary Wittie , Freescale Semiconductor, Inc. Austin, TX, USA
pp. 1

Automotive IC's: less testing, more prevention (PDF)

Davide Appello , STMicroelectronics s.r.l., Agrate Brianza, Italy
pp. 1-2

Statistical test: A new paradigm to improve test effectiveness & efficiency (PDF)

Peter M. O'Neill , Avago Technologies, Inc. Fort Collins, CO, USA
pp. 1-10

A universal DC to logic performance correlation (PDF)

Andrew Marshall , Texas Instruments Incorporated 13121 TI Boulevard, M/S 366, Dallas, 75243, USA
pp. 1-4

Principles and results of some test cost reduction methods for ASICs (PDF)

Peter Maxwell , Mobile Imaging Group Micron Technology, Inc., USA
pp. 1-5

Signature based diagnosis for logic BIST (PDF)

Wu-Tung Cheng , Mentor Graphics Corporation 8005 SW Boeckman Road Wilsonville, OR 97070, USA
Manish Sharma , Mentor Graphics Corporation 8005 SW Boeckman Road Wilsonville, OR 97070, USA
Thomas Rinderknecht , Mentor Graphics Corporation 8005 SW Boeckman Road Wilsonville, OR 97070, USA
Liyang Lai , Mentor Graphics Corporation 8005 SW Boeckman Road Wilsonville, OR 97070, USA
Chris Hill , Mentor Graphics Corporation 8005 SW Boeckman Road Wilsonville, OR 97070, USA
pp. 1-9
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