The Community for Technology Leaders
2006 IEEE International Test Conference (2006)
Santa Clara, CA USA
Oct. 22, 2006 to Oct. 27, 2006
ISSN: 1089-3539
ISBN: 1-4244-0291-3
TABLE OF CONTENTS

X-Press Compactor for 1000x Reduction of Test Data (Abstract)

J. Rajski , Mentor Graphics Corporation, Wilsonville, OR, USA
J. Tyszer , Poznan University of Technology, ul. Piotrowo 3a, 60-965 Poznan, Poland
G. Mrugalski , Mentor Graphics Corporation, Wilsonville, OR, USA
W.-t. Cheng , Mentor Graphics Corporation, Wilsonville, OR, USA
N. Mukherjee , Mentor Graphics Corporation, Wilsonville, OR, USA
M. Kassab , Mentor Graphics Corporation, Wilsonville, OR, USA
pp. 1-10

Test Compression for FPGAs (Abstract)

Mehdi B. Tahoori , Electrical and Computer Engineering, Northeastern University. mtahoori@ece.neu.edu
Subhasish Mitra , Electrical Engineering, Stanford University. subh@stanford.edu
pp. 1-9

Pattern Pruner: Automatic Pattern Size Reduction Method that Uses Computational Intelligence-Based Testing (Abstract)

Eric Liau Chee Hong , Infineon Technologies AG, Am Campeon 1-12, D-85579, Neubiberg, Germany. Email: eric.liau@infineon.com
Manfred Menke , Infineon Technologies AG, Am Campeon 1-12, D-85579, Neubiberg, Germany
Thomas Janik , Infineon Technologies AG, Am Campeon 1-12, D-85579, Neubiberg, Germany
Doris Schmitt-Landsiedel , Technische Universität München Theresienstr. 90, Gebäude N3, 80290 Munich Germany. Email: dsl@tum.de
pp. 1-10

Prospects for Wafer-Level Testing of Gigascale Chips with Electrical and Optical I/O Interconnects (Abstract)

Hiren D. Thacker , School of Electrical and Computer Engineering, Georgia Institute of Technology, Microelectronics Research Center, Atlanta, Georgia, USA
James D. Meindl , School of Electrical and Computer Engineering, Georgia Institute of Technology, Microelectronics Research Center, Atlanta, Georgia, USA
pp. 1-7

Embedded Memory Diagnosis: An Industrial Workflow (Abstract)

Davide Appello , STMicroelectronics, Agrate Brianza (MI), Italy
Vincenzo Tancorre , STMicroelectronics, Agrate Brianza (MI), Italy
Paolo Bernardi , Dipartimento di Automatica e Informatica - Politecnico di Torino, Torino, Italy
Michelangelo Grosso , Dipartimento di Automatica e Informatica - Politecnico di Torino, Torino, Italy
Maurizio Rebaudengo , Dipartimento di Automatica e Informatica - Politecnico di Torino, Torino, Italy
Matteo Sonza Reorda , Dipartimento di Automatica e Informatica - Politecnico di Torino, Torino, Italy
pp. 1-9

Combinational Logic Soft Error Correction (Abstract)

Subhasish Mitra , Stanford University, Stanford, CA
Ming Zhang , Intel Corp., Folsom, CA
Saad Waqas , Intel Corp., Folsom, CA
Norbert Seifert , Intel Corp., Hillsboro, OR
Balkaran Gill , Intel Corp., Hillsboro, OR
Kee Sup Kim , Intel Corp., Folsom, CA
pp. 1-9

A Robust, Self-Tuning CMOS Circuit for Built-in Go/No-Go Testing of Synthesizer Phase Noise (Abstract)

Erdem S. Erdogan , Department of Electrical & Computer Engineering, Duke University
Sule Ozev , Department of Electrical & Computer Engineering, Duke University
pp. 1-10

Testing MRAM for Write Disturbance Fault (Abstract)

Chin-lung Su , Department of Electrical Engineering, National Tsing Hua University, Hsinchu, Taiwan 30013, ROC
Chih-wea Tsai , Department of Electrical Engineering, National Tsing Hua University, Hsinchu, Taiwan 30013, ROC
Cheng-wen Wu , Department of Electrical Engineering, National Tsing Hua University, Hsinchu, Taiwan 30013, ROC
Chien-chung Hung , Electronics Research and Service Organization, Industrial Technology Research Institute, Hsinchu, Taiwan 30013, ROC
Young-shying Chen , Electronics Research and Service Organization, Industrial Technology Research Institute, Hsinchu, Taiwan 30013, ROC
Ming-jer Kao , Electronics Research and Service Organization, Industrial Technology Research Institute, Hsinchu, Taiwan 30013, ROC
pp. 1-9

An Accelerated Jitter Tolerance Test Technique on Ate for 1.5GB/S and 3GB/S Serial-ATA (Abstract)

Y. Fan , Agere Systems, 1110 American Parkway NE, Allentown, Pennsylvania 18109
Y. Cai , Agere Systems, 1110 American Parkway NE, Allentown, Pennsylvania 18109. Email: yicai@agere.com
L. Fang , Agere Systems, 1110 American Parkway NE, Allentown, Pennsylvania 18109
A. Verma , Agere Systems, 1110 American Parkway NE, Allentown, Pennsylvania 18109
W. Burchanowski , Agere Systems, 1110 American Parkway NE, Allentown, Pennsylvania 18109
Z. Zilic , Department of ECE, McGill University
S. Kumar , Agere Systems, 1110 American Parkway NE, Allentown, Pennsylvania 18109
pp. 1-10

Managing test, yield, quality, and cost in fabless manufacturing model (PDF)

Chris Malachowsky , Co-Founder, NVIDIA Fellow and Senior Vice President, Engineering and Operations
pp. 12

The impact of globalization on test and the test engineer [Invited Address] (PDF)

Greg Jordan , Manufacturing Test Engineering, Cisco System, Inc.
pp. 13

On the need for convergence between design validation and test (PDF)

Siva Yerramilli , General Manager, Design and Technology Solutions (DTS), Technology and Manufacturing Group, Intel Corporation
pp. 14

It's not what you can make - It's what you can test (PDF)

W. Robert Daasch , Professor, Electrical and Computer Engineering, Portland State University
pp. 15

What is DFM & DFY and Why Should I Care ? (PDF)

Rajesh Raina , Freescale Semiconductor, 7700 W. Parmer Ln, Austin, TX 78729. rajesh.raina@freescale.com
pp. 1-9

Zero defect: Mission impossible? (PDF)

Erik Jan Marinissen , Philips Research Laboratories, IC Design - Digital Design & Test, High Tech Campus 5, M/S WAY 41, 5656 AE Eindhoven, The Netherlands. erik.jan.marinissen@philips.com
Sandeep Kumar Goel , Philips Research Laboratories, IC Design - Digital Design & Test, High Tech Campus 5, M/S WAY 41, 5656 AE Eindhoven, The Netherlands. sandeepkumar.goel@philips.com
pp. 1

Zero defect mission requires an arsenal (Abstract)

D. Migl , Freescale, Inc., Austin, TX
pp. 1-2

Zero Defects: Managing Variation & International In The Total Value Chain (Abstract)

R. van Rijsinge , Bus. Unit Automotive & Identification, Philips Semicond., Nijmegen
pp. 1-2

Role of test in yield learning for 65 nm and beyond (PDF)

Thomas Ho , Credence Systems Corporation
pp. 1-2

Role of test in yield learning for 65nm and beyond (PDF)

Sanjiv Taneja , Vice President, General Manager, Encounter Test, Cadence Design Systems, Inc.
pp. 1
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