Exact aliasing computation for RAM BIST (PDF)
Synthesized transparent BIST for detecting scrambled pattern-sensitive faults in RAMs (PDF)
Deterministic self-test of a high-speed embedded memory and logic processor subsystem (PDF)
Upset-tolerant CMOS SRAM using current monitoring: prototype and test experiments (PDF)
The use of linear models for the efficient and accurate testing of A/D converters (PDF)
Industrial relevance of analog IFA: a fact or a fiction (PDF)
A comparative analysis of input stimuli for testing mixed-signal LSIs based on current testing (PDF)
Arbitrary-precision signal generation for bandlimited mixed-signal testing (PDF)
A general purpose ATE based I/sub DDQ/ measurement circuit (PDF)
SiProbe-a new technology for wafer probing (PDF)
Parallel delay fault coverage and test quality evaluation (PDF)
Non-robust versus robust [test generation] (PDF)
Test vector generation for parametric path delay faults (PDF)
Classification and test generation for path-delay faults using single stuck-fault tests (PDF)
Test generation and design for test for a large multiprocessing DSP (PDF)
Testability, debuggability, and manufacturability features of the UltraSPARC-I microprocessor (PDF)
Overview of PowerPC 620 multiprocessor verification strategy (PDF)
Structured design-for-debug-the SuperSPARC II methodology and implementation (PDF)
A novel low-cost approach to MCM interconnect test (PDF)
Integrated test solutions and test economics for MCMs (PDF)
A comparison of test requirements, methods, and results for seven MCM products (PDF)
Distributed probabilistic diagnosis of MCMs on large area substrates (PDF)
Matching models to real life for defect reduction (PDF)
Test SPC: a process to improve test system integrity (PDF)
User application of statistical process monitor techniques to ASIC critical parameters (PDF)
A test data collection system for uniform data analysis (PDF)
Coping with re-usability using sequential ATPG: a practical case study (PDF)
Low-complexity fault simulation under the multiple observation time testing approach (PDF)
A fault model and a test method for analog fuzzy logic circuits (PDF)
A designer's view of chip test (PDF)
Advantages of high level test synthesis over design for test (PDF)
Is high level test synthesis just design for test? (PDF)
The many faces of test synthesis (PDF)
The case for contract manufacturing (PDF)
Contract manufacturing: how much can they do? (PDF)
Re-examining the needs of the mixed-signal test community (PDF)
Stuck-at faults, PPMs rejects or? What do the SIA roadmaps say? (PDF)
The final barriers to widespread use of I/sub DDQ/ testing (PDF)
Test quality: required stuck-at fault coverage with the use of I/sub DDQ/ testing (PDF)
High-performance circuit testing with slow-speed testers (PDF)
Avoiding unknown states when scanning mutually exclusive latches (PDF)
Supplying known good die for MCM applications using low cost embedded testing (PDF)
IC performance prediction system (PDF)
An approach for designing total-dose tolerant MCMs based on current monitoring (PDF)
Improving DSP-based measurements with spectral interpolation (PDF)
THD and SNR tests using the simplified Volterra series with adaptive algorithms (PDF)
Improvement of the defect level of microcomputer LSI testing (PDF)
In-system testing of cache memories (PDF)
Towards 100% testable FIR digital filters (PDF)
An efficient and economic partitioning approach for testability (PDF)
A new method for partial scan design based on propagation and justification requirements of faults (PDF)
On combining design for testability techniques (PDF)
MCM quality and cost analysis using economics models (PDF)
Study on the costs of on-site VLSI testing (PDF)
The P1149.4 Mixed Signal Test Bus: costs and benefits (PDF)
A gate-array-based 666 MHz VLSI test system (PDF)
A low-cost high-performance CMOS timing vernier for ATE (PDF)
Evaluating waveform generation capabilities of VLSI test systems (PDF)
IDDQ testing of CMOS opens: an experimental study (PDF)
Production I/sub DDQ/ testing with passive current compensation (PDF)
Finding defects with fault models (PDF)
Timing-driven test point insertion for full-scan and partial-scan BIST (PDF)
Test point insertion for an area efficient BIST (PDF)
Performance driven BIST technique for random logic (PDF)
I/sub DDQ/ and voltage testable CMOS flip-flop configurations (PDF)
A detailed analysis of GOS defects in MOS transistors: testing implications at circuit level (PDF)
Inductive contamination analysis (ICA) with SRAM application (PDF)
Algorithmic extraction of BSDL from 1149.1-compliant sample ICs (PDF)
Integration of IEEE STD.11149.1 and mixed-signal test architectures (PDF)
Improving board and system test: a proposal to integrate boundary scan and I/sub DDQ/ (PDF)
High-level test generation using symbolic scheduling (PDF)
Hierarchical functional fault simulation for high-level synthesis (PDF)
Functional tests for scan chain latches (PDF)
On efficiently and reliably achieving low defective part levels (PDF)
Yield learning via functional test data (PDF)
Failure analysis for full-scan circuits (PDF)
A discussion of methods for measuring low-amplitude jitter (PDF)
An experimental chip to evaluate test techniques: chip and experiment design (PDF)
An experimental chip to evaluate test techniques experiment results (PDF)
Using the right tools and techniques leads to successful testing of MCMs (PDF)
Synthesis of mapping logic for generating transformed pseudo-random patterns for BIST (PDF)
Synthesis and retiming for the pseudo-exhaustive BIST of synchronous sequential circuits (PDF)
Test synthesis in the behavioral domain (PDF)
Software test data generation using the chaining approach (PDF)
From hardware to software testability (PDF)
On the use of neural networks to guide software testing activities (PDF)
Dynamic program complexity and software testing (PDF)
Test synthesis: from wishful thinking to reality (PDF)
Plug & play I/sub DDQ/ monitoring with QTAG (PDF)
IntegraTEST: the new wave in mixed-signal test (PDF)
Dynamic test emulation for EDA-based mixed-signal test development automation (PDF)
Report on a pilot project successfully implementing a design-to-test methodology (PDF)
A routing testing of a VLSI massively parallel machine based on IEEE 1149.1 (PDF)
A secure data transmission scheme for 1149.1 backplane test bus (PDF)
Leave the wires to last-functional evaluation of the IEEE Std 1149.5 module test and maintenance bus (PDF)
Cost-effective system-level test strategies (PDF)
A methodology to design efficient BIST test pattern generators (PDF)
An effective BIST scheme for Booth multipliers (PDF)
Optimal space compaction of test responses (PDF)
Implementing 1149.1 in the PowerPC RISC microprocessor family (PDF)
Compiled code dynamic worst case timing simulation tracking multiple causality (PDF)
Challenging the "high performance-high cost" paradigm in test (PDF)
A single board test system: changing the test paradigm (PDF)
A Tester for Design (TFD) (PDF)
Transient power supply current testing of digital CMOS circuits (PDF)
Intel386 EX embedded processor I/sub DDQ/ testing (PDF)
On the effect of I/sub SSQ/ testing in reducing early failure rate (PDF)
Solving known good die (and substrate) test issues (PDF)
Electrical troubleshooting, diagnostics, and repair of multichip modules (PDF)
STIL from the users perspective (PDF)
It's DFT, boundary scan and life cycle benefits (PDF)
Cutting the cost of test; the value-added way (PDF)
Optimizing product profitability-the test way (PDF)
Deep submicron: is test up to the challenge? (PDF)
What's so different about deep-submicron test? (PDF)
Finding I/O faults on in-circuit ICs using parasitic transistor tests (PDF)
New challenges-old roots [telecommunication systems testing] (PDF)
A built-in self-test strategy for wireless communication systems (PDF)
End-to-end test strategy for wireless systems (PDF)
Testing a switching memory in a telecommunication system (PDF)
Automated 1.5 GHz SONET characterization (PDF)
Development of an ATE test station for mixed CATV/TELCO products (PDF)
Optimizing test strategies for SONET/SDH/ATM network element manufacturing (PDF)
End-to-end performance measurement for interactive multimedia television (PDF)
Linking diagnostic software to hardware self test in telecom systems (PDF)
A new hardware fault insertion scheme for system diagnostics verification (PDF)
Author index (PDF)
