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Proceedings of 1995 IEEE International Test Conference (ITC) (1995)
Washington, DC, USA
Oct. 21, 1995 to Oct. 25, 1995
ISSN: 1089-3539
ISBN: 0-7803-2992-9
TABLE OF CONTENTS

Exact aliasing computation for RAM BIST (PDF)

O. Kebichi , Reliable Integrated Syst. Group, TIMA/INPG, Grenoble, France
M. Nicolaidis , Reliable Integrated Syst. Group, TIMA/INPG, Grenoble, France
pp. 13-22

Synthesized transparent BIST for detecting scrambled pattern-sensitive faults in RAMs (PDF)

B.F. Cockburn , Dept. of Electr. Eng., Alberta Univ., Edmonton, Alta., Canada
Y.-F.N. Sat , Dept. of Electr. Eng., Alberta Univ., Edmonton, Alta., Canada
pp. 23-32

Deterministic self-test of a high-speed embedded memory and logic processor subsystem (PDF)

L. Ternullo , Microelectron. Div., IBM Corp., Essex Junction, VT, USA
R.D. Adams , Microelectron. Div., IBM Corp., Essex Junction, VT, USA
J. Connor , Microelectron. Div., IBM Corp., Essex Junction, VT, USA
G.S. Koch , Microelectron. Div., IBM Corp., Essex Junction, VT, USA
pp. 33-44

Upset-tolerant CMOS SRAM using current monitoring: prototype and test experiments (PDF)

T. Calin , TIMA/INPG, Grenoble, France
F.L. Vargas , TIMA/INPG, Grenoble, France
M. Nicolaidis , TIMA/INPG, Grenoble, France
pp. 45-53

The use of linear models for the efficient and accurate testing of A/D converters (PDF)

P.D. Capofreddi , Integrated Circuits Lab., Stanford Univ., CA, USA
B.A. Wooley , Integrated Circuits Lab., Stanford Univ., CA, USA
pp. 54-60

Industrial relevance of analog IFA: a fact or a fiction (PDF)

M. Sachdev , Philips Res. Lab., Eindhoven, Netherlands
B. Atzema , Philips Res. Lab., Eindhoven, Netherlands
pp. 61-70

A comparative analysis of input stimuli for testing mixed-signal LSIs based on current testing (PDF)

Y. Miura , Dept. of Electron. & Inf. Eng., Tokyo Metropolitan Univ., Japan
pp. 71-77

Arbitrary-precision signal generation for bandlimited mixed-signal testing (PDF)

X. Haurie , Dept. of Electr. Eng., McGill Univ., Montreal, Que., Canada
G.W. Roberts , Dept. of Electr. Eng., McGill Univ., Montreal, Que., Canada
pp. 78-86

Visualizing quality (PDF)

S. Max , LTX Corp., Westwood, MA, USA
pp. 87-96

A general purpose ATE based I/sub DDQ/ measurement circuit (PDF)

G.H. Johnson , Megatest Corp., Fridley, MN, USA
J.B. Wilstrup , Megatest Corp., Fridley, MN, USA
pp. 97-105

SiProbe-a new technology for wafer probing (PDF)

K.F. Zimmermann , Contact Technol., Newbury Park, CA, USA
pp. 106-112

Parallel delay fault coverage and test quality evaluation (PDF)

I. Pramanick , Silicon Graphics Inc., Mountain View, CA, USA
pp. 113-122

Non-robust versus robust [test generation] (PDF)

A. Pierzynska , Sch. of Comput. Sci., Simon Fraser Univ., Burnaby, BC, Canada
S. Pilarski , Sch. of Comput. Sci., Simon Fraser Univ., Burnaby, BC, Canada
pp. 123-131

Test vector generation for parametric path delay faults (PDF)

M. Sivaraman , Carnegie Mellon Univ., Pittsburgh, PA, USA
A.J. Strojwas , Carnegie Mellon Univ., Pittsburgh, PA, USA
pp. 132-138

Classification and test generation for path-delay faults using single stuck-fault tests (PDF)

M.A. Gharaybeh , Dept. of Electr. & Comput. Eng., Rutgers Univ., Piscataway, NJ, USA
M.L. Bushnell , Dept. of Electr. & Comput. Eng., Rutgers Univ., Piscataway, NJ, USA
pp. 139-148

Test generation and design for test for a large multiprocessing DSP (PDF)

G. Hetherington , Texas Instrum. Ltd., Northampton, UK
G. Sutton , Texas Instrum. Ltd., Northampton, UK
pp. 149-156

Testability, debuggability, and manufacturability features of the UltraSPARC-I microprocessor (PDF)

M.E. Levitt , SPARC Technol. Bus., Sun Microsyst. Inc., Mountain View, CA, USA
S. Nori , SPARC Technol. Bus., Sun Microsyst. Inc., Mountain View, CA, USA
S. Narayanan , SPARC Technol. Bus., Sun Microsyst. Inc., Mountain View, CA, USA
G.P. Grewal , SPARC Technol. Bus., Sun Microsyst. Inc., Mountain View, CA, USA
pp. 157-166

Overview of PowerPC 620 multiprocessor verification strategy (PDF)

Jen-Tien Yen , IBM Corp., Austin, TX, USA
M. Sullivan , IBM Corp., Austin, TX, USA
pp. 167-174

Structured design-for-debug-the SuperSPARC II methodology and implementation (PDF)

Hong Hao , Sun Microsyst. Inc., Mountain View, CA, USA
R. Avra , Sun Microsyst. Inc., Mountain View, CA, USA
pp. 175-183

A novel low-cost approach to MCM interconnect test (PDF)

B.C. Kim , Sch. of Electr. & Comput. Eng., Georgia Inst. of Technol., Atlanta, GA, USA
A. Chatterjee , Sch. of Electr. & Comput. Eng., Georgia Inst. of Technol., Atlanta, GA, USA
M. Swaminathan , Sch. of Electr. & Comput. Eng., Georgia Inst. of Technol., Atlanta, GA, USA
D.E. Schimmel , Sch. of Electr. & Comput. Eng., Georgia Inst. of Technol., Atlanta, GA, USA
pp. 184-192

Integrated test solutions and test economics for MCMs (PDF)

K.T. Kornegay , Sch. of Electr. & Comput. Eng., Purdue Univ., West Lafayette, IN, USA
K. Roy , Sch. of Electr. & Comput. Eng., Purdue Univ., West Lafayette, IN, USA
pp. 193-201

A comparison of test requirements, methods, and results for seven MCM products (PDF)

A. Flint , Semicond. Products Sector, Motorola Inc., Tempe, AZ, USA
pp. 202-207

Distributed probabilistic diagnosis of MCMs on large area substrates (PDF)

K. Sasidhar , Sch. of Electr. & Comput. Eng., Georgia Inst. of Technol., Atlanta, GA, USA
A. Chatterjee , Sch. of Electr. & Comput. Eng., Georgia Inst. of Technol., Atlanta, GA, USA
pp. 208-216

Test SPC: a process to improve test system integrity (PDF)

W. Benitez , Semicond. Div., Texas Instrum., USA
D. Marrero , Semicond. Div., Texas Instrum., USA
D. Mirizzi , Semicond. Div., Texas Instrum., USA
D. Ohmart , Semicond. Div., Texas Instrum., USA
pp. 224-232

User application of statistical process monitor techniques to ASIC critical parameters (PDF)

A.M. Ijaz , Tandem Comput. Inc., Cupertino, CA, USA
E.R. Hnatek , Tandem Comput. Inc., Cupertino, CA, USA
pp. 233-241

A test data collection system for uniform data analysis (PDF)

S.D. Shaye , LTX Corp., Westwood, MA, USA
pp. 242-251

Coping with re-usability using sequential ATPG: a practical case study (PDF)

J. van Sas , Alcatel Bell Telephone, Antwerp, Belgium
E. Huyskens , Alcatel Bell Telephone, Antwerp, Belgium
H. Naert , Alcatel Bell Telephone, Antwerp, Belgium
pp. 252-261

DFT & ATPG: together again (PDF)

B. Mathew , MIPS Technol. Inc., Mountain View, CA, USA
pp. 262-271

Low-complexity fault simulation under the multiple observation time testing approach (PDF)

I. Pomeranz , Dept. of Electr. & Comput. Eng., Iowa Univ., Iowa City, IA, USA
S.M. Reddy , Dept. of Electr. & Comput. Eng., Iowa Univ., Iowa City, IA, USA
pp. 272-281

A fault model and a test method for analog fuzzy logic circuits (PDF)

S. Weiner , Inst. fur Theor. Elektrotech., Hannover Univ., Germany
pp. 282-291

A designer's view of chip test (PDF)

T.L. Anderson , Adv. Micro Devices Inc., Sunnyvale, CA, USA
pp. 292

Advantages of high level test synthesis over design for test (PDF)

R.K. Roy , C&C Res. Labs., NEC Res. Inst., Princeton, NJ, USA
pp. 293

Is high level test synthesis just design for test? (PDF)

C. Landrault , LIRMM, Montpellier, France
M.-L. Flottes , LIRMM, Montpellier, France
B. Rouzeyre , LIRMM, Montpellier, France
pp. 294

The many faces of test synthesis (PDF)

P.C. Maxwell , Integrated Circuit Bus. Div., Hewlett-Packard Co., USA
pp. 295

The case for contract manufacturing (PDF)

R. Hassig , AVEX Electron. Inc., Huntsville, AL, USA
pp. 296

Contract manufacturing: how much can they do? (PDF)

T. Langford , Symbiosis Logic, Wichita, KS, USA
pp. 297

Re-examining the needs of the mixed-signal test community (PDF)

G.W. Roberts , Dept. of Electr. Eng., McGill Univ., Montreal, Que., Canada
pp. 298

Stuck-at faults, PPMs rejects or? What do the SIA roadmaps say? (PDF)

K. Baker , Philips Res. Lab., Eindhoven, Netherlands
pp. 299

The final barriers to widespread use of I/sub DDQ/ testing (PDF)

J.M. Acken , CrossCheck Technol. Inc., San Jose, CA, USA
pp. 300

High-performance circuit testing with slow-speed testers (PDF)

V.D. Agrawal , AT&T Bell Labs., Murray Hill, NJ, USA
pp. 302-310

A hierarchical, design-for-testability (DFT) methodology for the rapid prototyping of application-specific signal processors (RASSP) (PDF)

R. Sedmak , Lockheed Martin Adv. Technol. Labs., USA
J. Evans , Lockheed Martin Adv. Technol. Labs., USA
pp. 319-327

Supplying known good die for MCM applications using low cost embedded testing (PDF)

A. Frisch , Tektronix Inc., Beaverton, OR, USA
M. Aigner , Tektronix Inc., Beaverton, OR, USA
T. Almy , Tektronix Inc., Beaverton, OR, USA
pp. 328-335

IC performance prediction system (PDF)

V. Ramakrishnan , Intel Corp., Santa Clara, CA, USA
pp. 336-344

An approach for designing total-dose tolerant MCMs based on current monitoring (PDF)

F. Vargas , TIMA/INPG Lab., Grenoble, France
M. Nicolaidis , TIMA/INPG Lab., Grenoble, France
pp. 345-354

Improving DSP-based measurements with spectral interpolation (PDF)

M. Burns , Texas Instrum. Inc., Dallas, TX, USA
pp. 355-363

THD and SNR tests using the simplified Volterra series with adaptive algorithms (PDF)

L.S.L. Hsieh , AT&T Bell Labs., Allentown, PA, USA
A. Grochowski , AT&T Bell Labs., Allentown, PA, USA
pp. 364-369

Improvement of the defect level of microcomputer LSI testing (PDF)

J. Hirase , Matsushita Electron. Corp., Japan
pp. 377-383

In-system testing of cache memories (PDF)

J. Sosnowski , Inst. of Comput. Sci., Warsaw Univ. of Technol., Poland
pp. 384-393

Towards 100% testable FIR digital filters (PDF)

L. Goodby , Dept. of Electr. & Comput. Eng., California Univ., San Diego, La Jolla, CA, USA
A. Orailoglu , Dept. of Electr. & Comput. Eng., California Univ., San Diego, La Jolla, CA, USA
pp. 394-402

An efficient and economic partitioning approach for testability (PDF)

Xinli Gu , Dept. of Comput. & Inf. Sci., Linkoping Univ., Sweden
K. Kuchcinski , Dept. of Comput. & Inf. Sci., Linkoping Univ., Sweden
Zebo Peng , Dept. of Comput. & Inf. Sci., Linkoping Univ., Sweden
pp. 403-412

On combining design for testability techniques (PDF)

P.S. Parikh , AT&T Bell Labs., Naperville, IL, USA
pp. 423-429

Study on the costs of on-site VLSI testing (PDF)

J. Hirase , Matsushita Electron. Corp., Japan
pp. 438-443

The P1149.4 Mixed Signal Test Bus: costs and benefits (PDF)

S. Sunter , Telecom Microelectron. Centre, Northern Telecom Electron. Ltd., Ottawa, Ont., Canada
pp. 444-450

A gate-array-based 666 MHz VLSI test system (PDF)

S. Kikuchi , Lab. of Production Eng. Res., Hitachi Ltd., Kanagawa, Japan
Y. Hayashi , Lab. of Production Eng. Res., Hitachi Ltd., Kanagawa, Japan
T. Suga , Lab. of Production Eng. Res., Hitachi Ltd., Kanagawa, Japan
pp. 451-458

A low-cost high-performance CMOS timing vernier for ATE (PDF)

J. Chapman , Credence Syst. Corp., Fremont, CA, USA
J. Currin , Credence Syst. Corp., Fremont, CA, USA
S. Payne , Credence Syst. Corp., Fremont, CA, USA
pp. 459-468

Evaluating waveform generation capabilities of VLSI test systems (PDF)

M.G. Davis , LTX/Trillium, San Jose, CA, USA
pp. 469-478

IDDQ testing of CMOS opens: an experimental study (PDF)

A.D. Singh , Dept. of Electr. Eng., Auburn Univ., AL, USA
H. Rasheed , Dept. of Electr. Eng., Auburn Univ., AL, USA
pp. 479-489

Production I/sub DDQ/ testing with passive current compensation (PDF)

G.A. Maston , Div. of Application Specific Integrated Circuits, Motorola Inc., Chandler, AZ, USA
pp. 490-497

Finding defects with fault models (PDF)

R.C. Aitken , Design Technol. Centre, Hewlett-Packard Co., Palo Alto, CA, USA
pp. 498-505

Timing-driven test point insertion for full-scan and partial-scan BIST (PDF)

Kwan-Ting Cheng , Dept. of Electr. & Comput. Eng., California Univ., Santa Barbara, CA, USA
pp. 506-514

Test point insertion for an area efficient BIST (PDF)

C. Schotten , Inst. for Int. Syst. in Signal Process., Aachen Univ. of Technol., Germany
H. Meyr , Inst. for Int. Syst. in Signal Process., Aachen Univ. of Technol., Germany
pp. 515-523

Performance driven BIST technique for random logic (PDF)

C.A. Njinda , Adv. Micro Devices Inc., Sunnyvale, CA, USA
pp. 524-533

I/sub DDQ/ and voltage testable CMOS flip-flop configurations (PDF)

M. Sachdev , Philips Res. Lab., Eindhoven, Netherlands
pp. 534-543

A detailed analysis of GOS defects in MOS transistors: testing implications at circuit level (PDF)

J. Segura , Dept. of Phys., Balearic Islands Univ., Palma de Mallorca, Spain
C. De Benito , Dept. of Phys., Balearic Islands Univ., Palma de Mallorca, Spain
A. Rubio , Dept. of Phys., Balearic Islands Univ., Palma de Mallorca, Spain
pp. 544-551

Inductive contamination analysis (ICA) with SRAM application (PDF)

J. Khare , Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
W. Maly , Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
pp. 552-560

Algorithmic extraction of BSDL from 1149.1-compliant sample ICs (PDF)

D.W. Raymond , Assembly Test Group, Teradyne Inc., USA
D.E. Wedge , Assembly Test Group, Teradyne Inc., USA
P.J. Stringer , Assembly Test Group, Teradyne Inc., USA
H.W. Ng , Assembly Test Group, Teradyne Inc., USA
S.T. Jennings , Assembly Test Group, Teradyne Inc., USA
C.T. Pynn , Assembly Test Group, Teradyne Inc., USA
W. Soule , Assembly Test Group, Teradyne Inc., USA
pp. 561-568

Integration of IEEE STD.11149.1 and mixed-signal test architectures (PDF)

D.J. Cheek , Dept. of Electr. & Comput. Eng., Colorado Univ., Colorado Springs, CO, USA
R. Dandapani , Dept. of Electr. & Comput. Eng., Colorado Univ., Colorado Springs, CO, USA
pp. 569-576

Improving board and system test: a proposal to integrate boundary scan and I/sub DDQ/ (PDF)

D. Reed , Lockheed Martin Space Oper., Kennedy Space Centre, FL, USA
pp. 577-585

High-level test generation using symbolic scheduling (PDF)

M.C. Hansen , Design Autom. Oper., Delco Electron. Corp., Kokomo, IN, USA
pp. 586-595

Hierarchical functional fault simulation for high-level synthesis (PDF)

M. Kassab , MACS Lab., McGill Univ., Montreal, Que., Canada
pp. 596-605

Functional tests for scan chain latches (PDF)

S.R. Makar , Center for Reliable Comput., Stanford Univ., CA, USA
E.J. McCluskey , Center for Reliable Comput., Stanford Univ., CA, USA
pp. 606-615

Yield learning via functional test data (PDF)

Young-Jun Kwon , Dept. of Comput. Sci., Texas A&M Univ., College Station, TX, USA
D.M.H. Walker , Dept. of Comput. Sci., Texas A&M Univ., College Station, TX, USA
pp. 626-635

Failure analysis for full-scan circuits (PDF)

K. De , LSI Logic Corp., Milpitas, CA, USA
A. Gunda , LSI Logic Corp., Milpitas, CA, USA
pp. 636-645

A discussion of methods for measuring low-amplitude jitter (PDF)

M.K. Williams , Amherst Syst. Associates Inc., MA, USA
pp. 646-652

An experimental chip to evaluate test techniques experiment results (PDF)

S.C. Ma , Center for Reliable Comput., Stanford Univ., CA, USA
P. Franco , Center for Reliable Comput., Stanford Univ., CA, USA
E.J. McCluskey , Center for Reliable Comput., Stanford Univ., CA, USA
pp. 663-672

Using the right tools and techniques leads to successful testing of MCMs (PDF)

A. Flint , Semicond. Products Sector, Motorola Inc., Tempe, AZ, USA
pp. 673

Synthesis of mapping logic for generating transformed pseudo-random patterns for BIST (PDF)

N.A. Touba , Center for Reliable Comput., Stanford Univ., CA, USA
E.J. McCluskey , Center for Reliable Comput., Stanford Univ., CA, USA
pp. 674-682

Synthesis and retiming for the pseudo-exhaustive BIST of synchronous sequential circuits (PDF)

S. Lejmi , Ecole Polytech. de Montreal, Que., Canada
B. Kaminska , Ecole Polytech. de Montreal, Que., Canada
B. Ayari , Ecole Polytech. de Montreal, Que., Canada
pp. 683-692

Test synthesis in the behavioral domain (PDF)

C. Papachristou , Dept. of Comput. Eng., Case Western Reserve Univ., Cleveland, OH, USA
J. Carletta , Dept. of Comput. Eng., Case Western Reserve Univ., Cleveland, OH, USA
pp. 693-702

Software test data generation using the chaining approach (PDF)

R. Ferguson , Dept. of Comput. Sci., Lawrence Technol. Univ., USA
pp. 703-709

From hardware to software testability (PDF)

Y. Le Traon , Lab. de Genie Inf., IMAG, Grenoble, France
C. Robach , Lab. de Genie Inf., IMAG, Grenoble, France
pp. 710-719

On the use of neural networks to guide software testing activities (PDF)

C. Anderson , Dept. of Comput. Sci., Colorado State Univ., Fort Collins, CO, USA
A. Von Mayrhauser , Dept. of Comput. Sci., Colorado State Univ., Fort Collins, CO, USA
pp. 720-729

Dynamic program complexity and software testing (PDF)

J.C. Munson , Dept. of Comput. Sci., Idaho Univ., Moscow, ID, USA
G.A. Hall , Dept. of Comput. Sci., Idaho Univ., Moscow, ID, USA
pp. 730-737

Test synthesis: from wishful thinking to reality (PDF)

K.N. Ruparel , Apple Comput. Inc., Cupertino, CA, USA
pp. 738

Plug & play I/sub DDQ/ monitoring with QTAG (PDF)

K. Baker , Philips Res. Lab., Eindhoven, Netherlands
T.F. Waayers , Philips Res. Lab., Eindhoven, Netherlands
F.G.M. Bouwman , Philips Res. Lab., Eindhoven, Netherlands
M.J.W. Verstraelen , Philips Res. Lab., Eindhoven, Netherlands
pp. 739-749

IntegraTEST: the new wave in mixed-signal test (PDF)

B. Schneider , MicroLEX Syst., Hoersholm, Denmark
S. Soegaard , MicroLEX Syst., Hoersholm, Denmark
pp. 750-760

A routing testing of a VLSI massively parallel machine based on IEEE 1149.1 (PDF)

C. Aktouf , LGI-IMAG, Grenoble, France
C. Robach , LGI-IMAG, Grenoble, France
A. Marinescu , LGI-IMAG, Grenoble, France
pp. 781-788

A secure data transmission scheme for 1149.1 backplane test bus (PDF)

Wuudiann Ke , Eng. Res. Centre, AT&T Bell Labs., Princeton, NJ, USA
Duy Le , Eng. Res. Centre, AT&T Bell Labs., Princeton, NJ, USA
N. Jarwala , Eng. Res. Centre, AT&T Bell Labs., Princeton, NJ, USA
pp. 789-796

Cost-effective system-level test strategies (PDF)

D. Farren , Digital Equipment Scotland Ltd., Ayr, UK
pp. 807-813

A methodology to design efficient BIST test pattern generators (PDF)

Chih-Ang Chen , Dept. of Electr. Eng. Syst., Univ. of Southern California, Los Angeles, CA, USA
S.K. Gupta , Dept. of Electr. Eng. Syst., Univ. of Southern California, Los Angeles, CA, USA
pp. 814-823

An effective BIST scheme for Booth multipliers (PDF)

D. Gizopoulos , NCSR Demokritos, Athens, Greece
A. Paschalis , NCSR Demokritos, Athens, Greece
pp. 824-833

Optimal space compaction of test responses (PDF)

K. Chakrabarty , Adv. Comput. Archit. Lab., Michigan Univ., Ann Arbor, MI, USA
pp. 834-843

Implementing 1149.1 in the PowerPC RISC microprocessor family (PDF)

C. Pyron , Somerset Design Centre, Motorola Inc., Austin, TX, USA
pp. 844-850

Improved boundary scan design (PDF)

L. Whetsel , Texas Instrum. Inc., USA
pp. 851-860

Compiled code dynamic worst case timing simulation tracking multiple causality (PDF)

K.K. Varma , Mentor Graphics Corp., Wilsonville, OR, USA
pp. 861-869

Challenging the "high performance-high cost" paradigm in test (PDF)

U. Schoettmer , Hewlett-Packard GmbH, Boblingen, Germany
pp. 870-879

A Tester for Design (TFD) (PDF)

G.J. Lesmeister , ITLOPS Div., Credence Syst. Corp., Fremont, CA, USA
pp. 886-891

Intel386 EX embedded processor I/sub DDQ/ testing (PDF)

H. Ahuja , Semicond. Products Group, Intel Corp., Chandler, AZ, USA
D. Arriens , Semicond. Products Group, Intel Corp., Chandler, AZ, USA
B. Schneller , Semicond. Products Group, Intel Corp., Chandler, AZ, USA
V. Verma , Semicond. Products Group, Intel Corp., Chandler, AZ, USA
W. Whitman , Semicond. Products Group, Intel Corp., Chandler, AZ, USA
pp. 902-909

On the effect of I/sub SSQ/ testing in reducing early failure rate (PDF)

K.M. Wallquist , Philips Semicond., Albuquerque, NM, USA
pp. 910-915

Solving known good die (and substrate) test issues (PDF)

A.W. Righter , Multichip Module Applications Dept., Sandia Nat. Labs., Albuquerque, NM, USA
pp. 916

Electrical troubleshooting, diagnostics, and repair of multichip modules (PDF)

D.C. Keezer , Sch. of Electr. & Comput. Eng., Georgia Inst. of Technol., Atlanta, GA, USA
pp. 917

Required-a portable test standard (PDF)

L.D. Carpenter , Aeronaut. Radio Inc., USA
pp. 918

STIL from the users perspective (PDF)

G.A. Maston , Application Specific Integrated Circuits Div., Motorola Inc., Chandler, AZ, USA
pp. 919

It's DFT, boundary scan and life cycle benefits (PDF)

G. O'Donnell , Nat. Semicond. Corp., South Portland, ME, USA
pp. 920

Cutting the cost of test; the value-added way (PDF)

W.R. Simpson , Inst. for Defense Anal., Alexandria, VA, USA
pp. 921

Optimizing product profitability-the test way (PDF)

P. Varma , CrossCheck Technol. Inc., San Jose, CA, USA
pp. 922

Deep submicron: is test up to the challenge? (PDF)

K.M. Butler , Texas Instrum. Inc., Dallas, TX, USA
pp. 923

What's so different about deep-submicron test? (PDF)

C. Hunter , Somerset Design Centre, Motorola Inc., Austin, TX, USA
pp. 924

Capacitive leadframe testing (PDF)

T.T. Turner , Manuf. Test Div., Hewlett-Packard Co., USA
pp. 928

New challenges-old roots [telecommunication systems testing] (PDF)

J. Jamieson , Business Processes & Inf. Syst., Alcatel, Zaventem, Belgium
pp. 929

A built-in self-test strategy for wireless communication systems (PDF)

B.R. Veillette , Microelectron. & Comput. Syst. Lab., McGill Univ., Montreal, Que., Canada
G.W. Roberts , Microelectron. & Comput. Syst. Lab., McGill Univ., Montreal, Que., Canada
pp. 930-939

End-to-end test strategy for wireless systems (PDF)

M. Jarwala , AT&T Bell Labs., Princeton, NJ, USA
Duy Le , AT&T Bell Labs., Princeton, NJ, USA
M.S. Heutmaker , AT&T Bell Labs., Princeton, NJ, USA
pp. 940-946

Testing a switching memory in a telecommunication system (PDF)

S. Barbagallo , R&D Labs., Italtel Soc. Italiana Telecommun. SpA, Milan, Italy
pp. 947-956

Automated 1.5 GHz SONET characterization (PDF)

R. Tepper , Appl. Micro Circuits Corp., San Diego, CA, USA
pp. 957-965

Development of an ATE test station for mixed CATV/TELCO products (PDF)

M.T. Freeman , ScientificAtlanta Inc., Norcross, GA, USA
pp. 966-972

Optimizing test strategies for SONET/SDH/ATM network element manufacturing (PDF)

M. Hoogerbrugge , Queensferry Telecommun. Oper., Hewlett-Packard Ltd., South Queensferry, UK
pp. 973-978

Linking diagnostic software to hardware self test in telecom systems (PDF)

H. Hulvershorn , Northern Telecom Electron. Ltd., Ottawa, Ont., Canada
P. Soong , Northern Telecom Electron. Ltd., Ottawa, Ont., Canada
S. Adham , Northern Telecom Electron. Ltd., Ottawa, Ont., Canada
pp. 986-993

Author index (PDF)

pp. 1010
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