The Community for Technology Leaders
Proceedings of International Test Conference (1994)
Washington, DC, USA
Oct. 2, 1995 to Oct. 6, 1994
ISSN: 1089-3539
ISBN: 0-7803-2103-0
TABLE OF CONTENTS

Development of a solution for achieving known-good-die (PDF)

L. Prokopchak , AEHR Test Syst., Mountain View, CA, USA
pp. 15-21

Membrane probe technology for MCM Known-Good-Die (PDF)

T. Ueno , Hewlett-Packard Labs., Kanagawa, Japan
Y. Kondoh , Hewlett-Packard Labs., Kanagawa, Japan
pp. 22-29

High yield multichip modules based on minimal IC pretest (PDF)

W. Burdick , Corp. Res. & Dev., Gen. Electr. Co., Schenectady, NY, USA
W. Daum , Corp. Res. & Dev., Gen. Electr. Co., Schenectady, NY, USA
pp. 30-40

Feasibility study of smart substrate multichip modules (PDF)

A.E. Gattiker , Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
W. Maly , Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
pp. 41-49

Testability strategy of the Alpha AXP 21164 microprocessor (PDF)

D.K. Bhavsar , Digital Equipment Corp., Hudson, MA, USA
J.H. Edmondson , Digital Equipment Corp., Hudson, MA, USA
pp. 50-59

Testability features of the MC68060 microprocessor (PDF)

A.L. Crouch , Motorola Inc., Austin, TX, USA
M. Pressly , Motorola Inc., Austin, TX, USA
J. Circello , Motorola Inc., Austin, TX, USA
pp. 60-69

MicroSPARC: a case-study of scan based debug (PDF)

K. Holdbrook , Sun Microsyst. Inc., Mountain View, CA, USA
S. Joshi , Sun Microsyst. Inc., Mountain View, CA, USA
S. Mitra , Sun Microsyst. Inc., Mountain View, CA, USA
J. Petolino , Sun Microsyst. Inc., Mountain View, CA, USA
R. Raman , Sun Microsyst. Inc., Mountain View, CA, USA
M. Wong , Sun Microsyst. Inc., Mountain View, CA, USA
pp. 70-75

System test cost modelling based on event rate analysis (PDF)

D. Farren , Digital Equipment Scotland Ltd., Ayr, UK
pp. 84-92

ASIC test cost/strategy trade-offs (PDF)

D.L. Wheater , Microelectron. Div., IBM Corp., Essex Junction, VT, USA
P. Nigh , Microelectron. Div., IBM Corp., Essex Junction, VT, USA
J.T. Mechler , Microelectron. Div., IBM Corp., Essex Junction, VT, USA
L. Lacroix , Microelectron. Div., IBM Corp., Essex Junction, VT, USA
pp. 93-102

A test process optimization and cost modeling tool (PDF)

T.J. Moore , Digital Equipment Corp., Maynard, MA, USA
pp. 103-110

When does it make C to give up physical test access? (PDF)

D.A. Greene , AT&T Global Inf. Solutions, West Columbia, SC, USA
pp. 111-119

3B21D BIST/Boundary-Scan system diagnostic test story (PDF)

E.C. Behnke , AT&T Bell Labs., Naperville, IL, USA
pp. 120-126

Modeling for structured system interconnect test (PDF)

F.W. Angelotti , Application Bus. Syst. Div., IBM Corp., Rochester, MN, USA
pp. 127-133

System-level testability of hardware/software systems (PDF)

H.P.E. Vranken , Dept. of Electr. Eng., Eindhoven Univ. of Technol., Netherlands
M.P.J. Stevens , Dept. of Electr. Eng., Eindhoven Univ. of Technol., Netherlands
M.T.M. Segers , Dept. of Electr. Eng., Eindhoven Univ. of Technol., Netherlands
J.H.M.M. van Rhee , Dept. of Electr. Eng., Eindhoven Univ. of Technol., Netherlands
pp. 134-142

Fastpath: a path-delay test generator for standard scan designs (PDF)

B. Underwood , Semicond. Syst. Design Technol., Motorola Inc., USA
Wai-On Law , Semicond. Syst. Design Technol., Motorola Inc., USA
pp. 154-163

On path delay testing in a standard scan environment (PDF)

P. Varma , CrossCheck Technol. Inc., San Jose, CA, USA
pp. 164-173

Automated logic synthesis of random pattern testable circuits (PDF)

N.A. Touba , Dept. of Electr. Eng., Stanford Univ., CA, USA
E.J. McCluskey , Dept. of Electr. Eng., Stanford Univ., CA, USA
pp. 174-183

Transforming behavioral specifications to facilitate synthesis of testable designs (PDF)

S. Dey , C&C Res. Labs., NEC Res. Inst., Princeton, NJ, USA
M. Potkonjak , C&C Res. Labs., NEC Res. Inst., Princeton, NJ, USA
pp. 184-193

QTAG: a standard for test fixture based I/sub DDQ//I/sub SSQ/ monitors (PDF)

K. Baker , Philips Res. Lab., Eindhoven, Netherlands
pp. 194-202

Development of a class 1 QTAG monitor (PDF)

K. Baker , Philips Res. Lab., Eindhoven, Netherlands
pp. 213-222

A serially addressable, flexible current monitor for test fixture based I/sub DDQ//I/sub SSQ/ testing (PDF)

A. Hales , Design Autom. Div., Texas Instrum. Inc., Dallas, TX, USA
pp. 223-232

On the initialization of sequential circuits (PDF)

J.A. Wahbeh , IBM Corp., Hopewell Junction, NY, USA
pp. 233-239

An automatic test pattern generator for large sequential circuits based on Genetic Algorithms (PDF)

P. Prinetto , Dipartimento di Autom. e Inf., Politecnico di Torino, Italy
M. Rebaudengo , Dipartimento di Autom. e Inf., Politecnico di Torino, Italy
M. Sonza Reorda , Dipartimento di Autom. e Inf., Politecnico di Torino, Italy
pp. 240-249

ATPG for heat dissipation minimization during test application (PDF)

Seongmoon Wang , Univ. of Southern California, Los Angeles, CA, USA
S.K. Gupta , Univ. of Southern California, Los Angeles, CA, USA
pp. 250-258

Sequentially untestable faults identified without search ("simple implications beat exhaustive search!") (PDF)

M.A. Iyer , Dept. of Electr. & Comput. Eng., Illinois Inst. of Technol., Chicago, IL, USA
pp. 259-266

500 MHz testing on a 100 MHz tester (PDF)

D. Wimmers , Schlumberger Technol., San Jose, CA, USA
K. Sakaitani , Schlumberger Technol., San Jose, CA, USA
B. West , Schlumberger Technol., San Jose, CA, USA
pp. 273-278

Modeling the effect of ground bounce on noise margin (PDF)

M.S. Haydt , Santa Clara Univ., CA, USA
R. Owens , Santa Clara Univ., CA, USA
S. Mourad , Santa Clara Univ., CA, USA
pp. 279-285

Modular mixed signal testing: high speed or high resolution (PDF)

E. Kushnick , LTX Corp., Westwood, MA, USA
pp. 286-290

Built-in system test and fault location (PDF)

G.R. McLeod , GEC-Marconi Avionics, Edinburgh, UK
pp. 291-299

Environmental Stress Testing with Boundary-Scan (PDF)

D. Le , Eng. Res. Center, AT&T Bell Labs., Princeton, NJ, USA
I. Karolik , Eng. Res. Center, AT&T Bell Labs., Princeton, NJ, USA
pp. 307-313

Multi-frequency, multi-phase scan chain (PDF)

Kee Sup Kim , Microprocessor Products Group, Intel Corp., USA
L. Schultz , Microprocessor Products Group, Intel Corp., USA
pp. 323-330

A test clock reduction method for scan-designed circuits (PDF)

Jau-Shien Chang , Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan
Chen-Shang Lin , Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan
pp. 331-339

Hybrid design for testability combining scan and clock line control and method for test generation (PDF)

Sanghyeon Baeg , Comput. Eng. Res. Center, Texas Univ., Austin, TX, USA
W.A. Rogers , Comput. Eng. Res. Center, Texas Univ., Austin, TX, USA
pp. 340-349

In-system timing extraction and control through scan-based, test-access ports (PDF)

A. DeHon , Artificial Intelligence Lab., MIT, Cambridge, MA, USA
pp. 350-359

Testing high speed DRAMs (PDF)

J.A. Gasbarro , Rambus Inc., USA
pp. 361

Testing issues on high speed synchronous DRAMs (PDF)

Wha-Joon Lee , Memory Bus. Div., Samsung Electronics Co., Suwon, South Korea
pp. 363

Benchmarking (PDF)

K. Ruparel , Apple Comput. Inc., Cupertino, CA, USA
pp. 364

Potential solutions for benchmarking issues (PDF)

D. Sterba , Texas Instrum. Inc., USA
pp. 365

MCM test trade-offs (PDF)

J. Eastman , MCM Test & Stress Eng., IBM Corp. Microelectron. Div., USA
pp. 367

Aliasing-free signature analysis for RAM BIST (PDF)

V.N. Yarmolik , Reliable Integrated Syst. Group, TIMA/INPG, Grenoble, France
M. Nicolaidis , Reliable Integrated Syst. Group, TIMA/INPG, Grenoble, France
O. Kebichi , Reliable Integrated Syst. Group, TIMA/INPG, Grenoble, France
pp. 368-377

The PowerPC 603 microprocessor: an array built-in self test mechanism (PDF)

C. Hunter , Somerset Design Center, Motorola Inc., Austin, TX, USA
J. Slaton , Somerset Design Center, Motorola Inc., Austin, TX, USA
J. Eno , Somerset Design Center, Motorola Inc., Austin, TX, USA
R. Jessani , Somerset Design Center, Motorola Inc., Austin, TX, USA
pp. 388-394

Testing CMOS logic gates for: realistic shorts (PDF)

B. Chess , Dept. of Comput. Eng., California Univ., Santa Cruz, CA, USA
A. Freitas , Dept. of Comput. Eng., California Univ., Santa Cruz, CA, USA
F.J. Ferguson , Dept. of Comput. Eng., California Univ., Santa Cruz, CA, USA
T. Larrabee , Dept. of Comput. Eng., California Univ., Santa Cruz, CA, USA
pp. 395-402

A study of I/sub DDQ/ subset selection algorithms for bridging faults (PDF)

S. Chakravarty , Dept. of Comput. Sci., State Univ. of New York, Buffalo, NY, USA
P. Thadikaran , Dept. of Comput. Sci., State Univ. of New York, Buffalo, NY, USA
pp. 403-412

Defect classes-an overdue paradigm for CMOS IC testing (PDF)

C.F. Hawkins , Dept. of Electr. & Comput. Eng., New Mexico Univ., Albuquerque, NM, USA
pp. 413-425

A test methodology to support an ASEM MCM foundry (PDF)

T. Storey , Loral Federal Syst., Manassas, VA, USA
C. Lapihuska , Loral Federal Syst., Manassas, VA, USA
pp. 426-435

Test strategies for a family of complex MCMs (PDF)

A. Flint , Logic & Analog Technol. Group, Motorola Inc., Tempe, AZ, USA
pp. 436-445

Designing "dual personality" IEEE 1149.1 compliant multi-chip modules (PDF)

N. Jarwala , Eng. Res. Center, AT&T Bell Labs., Princeton, NJ, USA
pp. 446-455

A case-study in the use of scan in microSPARC testing and debug (PDF)

J. Katz , Sun Microsystems Inc., Mountain View, CA, USA
pp. 456-460

A hierarchical environment for interactive test engineering (PDF)

T. Burch , Dept. of Comput. Sci., Saarlandes Univ., Saarbrucken, Germany
J. Hartmann , Dept. of Comput. Sci., Saarlandes Univ., Saarbrucken, Germany
G. Hotz , Dept. of Comput. Sci., Saarlandes Univ., Saarbrucken, Germany
M. Krallmann , Dept. of Comput. Sci., Saarlandes Univ., Saarbrucken, Germany
U. Nikolaus , Dept. of Comput. Sci., Saarlandes Univ., Saarbrucken, Germany
pp. 461-470

Ensuring system traceability to international standards (PDF)

S. Max , LTX Corp., Westwood, MA, USA
pp. 471-480

GLFSR-a new test pattern generator for built-in-self-test (PDF)

D.K. Pradhan , Dept. of Comput. Sci., Texas A&M Univ., College Station, TX, USA
M. Chatterjee , Dept. of Comput. Sci., Texas A&M Univ., College Station, TX, USA
pp. 481-490

Design of an efficient weighted random pattern generation system (PDF)

R. Kapur , IBM Corp. Microelectron, Endicott, NY, USA
S. Patil , IBM Corp. Microelectron, Endicott, NY, USA
T.J. Snethen , IBM Corp. Microelectron, Endicott, NY, USA
pp. 491-500

Efficient test response compression for multiple-output circuits (PDF)

K. Chakrabarty , Dept. of Electr. Eng. & Comput. Sci., Michigan Univ., Ann Arbor, MI, USA
J.P. Hayes , Dept. of Electr. Eng. & Comput. Sci., Michigan Univ., Ann Arbor, MI, USA
pp. 501-510

ECC-on-SIMM test challenges (PDF)

T.J. Dell , IBM Corp. Microelectron. Div, Essex Junction, VT, USA
pp. 511-515

Automatic failure analysis system for high density DRAM (PDF)

Sang-Chul Oh , Memory Bus. Div., Samsung Electronics Co., Suwon, South Korea
Jae-Ho Kim , Memory Bus. Div., Samsung Electronics Co., Suwon, South Korea
Ho-Jeong Choi , Memory Bus. Div., Samsung Electronics Co., Suwon, South Korea
Si-Don Choi , Memory Bus. Div., Samsung Electronics Co., Suwon, South Korea
Ki-Tae Park , Memory Bus. Div., Samsung Electronics Co., Suwon, South Korea
Jong-Woo Park , Memory Bus. Div., Samsung Electronics Co., Suwon, South Korea
Wha-Joon Lee , Memory Bus. Div., Samsung Electronics Co., Suwon, South Korea
pp. 526-530

Defects, fault coverage, yield and cost, in board manufacturing (PDF)

M.M.V. Tegethoff , Hewlett-Packard Co., Fort Collins, CO, USA
pp. 539-547

HALT: bridging the gap between theory and practice (PDF)

C. Ascarrunz , Tandem Comput. Inc., Cupertino, CA, USA
pp. 548-554

Residual charge on the faulty floating gate CMOS transistor (PDF)

S. Johnson , Sch. of Eng., Durham Univ., UK
pp. 555-561

Variable supply voltage testing for analogue CMOS and bipolar circuits (PDF)

E. Bruls , Philips Res. Labs., Eindhoven, Netherlands
pp. 562-571

Is I/sub DDQ/ yield loss inevitable? (PDF)

S. Davidson , AT&T Bell Labs., Princeton, NJ, USA
pp. 572-579

A software architecture for mixed signal functional testing (PDF)

J.A. Masciola , GenRad Inc., Concord, MA, USA
G.K. Morgan , GenRad Inc., Concord, MA, USA
G.L. Templeton , GenRad Inc., Concord, MA, USA
pp. 580-586

A procedural interface to test (PDF)

G.A. Maston , Motorola Inc., Chandler, AZ, USA
pp. 587-593

An intelligent software-integrated environment of IC test (PDF)

Yuning Sun , Inst. of Comput. Technol., Acad. Sinica, Beijing, China
Xiaoming Wang , Inst. of Comput. Technol., Acad. Sinica, Beijing, China
WanChun Shi , Inst. of Comput. Technol., Acad. Sinica, Beijing, China
pp. 594-603

Parallel pattern fast fault simulation for three-state circuits and bidirectional I/O (PDF)

J.Th. van der Linden , Dept. of Electr. Eng., Delft Univ. of Technol., Netherlands
M.H. Konijnenburg , Dept. of Electr. Eng., Delft Univ. of Technol., Netherlands
A.J. van de Goor , Dept. of Electr. Eng., Delft Univ. of Technol., Netherlands
pp. 604-613

A hybrid fault simulator for synchronous sequential circuits (PDF)

R. Krieger , J.W. Goethe Univ., Frankfurt, Germany
B. Becker , J.W. Goethe Univ., Frankfurt, Germany
M. Keim , J.W. Goethe Univ., Frankfurt, Germany
pp. 614-623

Reduced scan shift: a new testing method for sequential circuits (PDF)

Y. Higami , Fac. of Eng., Osaka Univ., Japan
S. Kajihara , Fac. of Eng., Osaka Univ., Japan
K. Kinoshita , Fac. of Eng., Osaka Univ., Japan
pp. 624-630

An integrated approach for analog circuit testing with a minimum number of detected parameters (PDF)

M. Slamani , Dept. of Electr. Eng., Ecole Polytech. de Montreal, Que., Canada
B. Kaminska , Dept. of Electr. Eng., Ecole Polytech. de Montreal, Que., Canada
pp. 631-640

Analogue fault simulation based on layout dependent fault models (PDF)

R.J.A. Harvey , Dept. of Eng., Lancaster Univ., UK
A.M.D. Richardson , Dept. of Eng., Lancaster Univ., UK
pp. 641-649

An analog multi-tone signal generator for built-in-self-test applications (PDF)

A.K. Lu , Dept. of Electr. Eng., McGill Univ., Montreal, Que., Canada
G.W. Roberts , Dept. of Electr. Eng., McGill Univ., Montreal, Que., Canada
pp. 650-659

Low power mode and IEEE 1149.1 compliance: a low power solution (PDF)

A.L. Crouch , Motorola Inc., Austin, TX, USA
R. Ramus , Motorola Inc., Austin, TX, USA
pp. 660-669

An I/sub DDQ/ based built-in concurrent test technique for interconnects in a boundary scan environment (PDF)

Chauchin Su , Dept. of Electr. Eng., Nat. Central Univ., Chung-Li, Taiwan
Kychin Hwang , Dept. of Electr. Eng., Nat. Central Univ., Chung-Li, Taiwan
Shyh-Jye Jou , Dept. of Electr. Eng., Nat. Central Univ., Chung-Li, Taiwan
pp. 670-676

Fault injection boundary scan design for verification of fault tolerant systems (PDF)

S. Chau , Jet Propulsion Lab., California Inst. of Technol., Pasadena, CA, USA
pp. 677-682

Ultra hi-speed pin-electronics and test station using GaAs IC (PDF)

T. Sekino , Advantest Corp., Saitama, Japan
T. Okayasu , Advantest Corp., Saitama, Japan
pp. 683-690

Achieving /spl plusmn/30 ps accuracy in the ATE environment (PDF)

D. Petrich , Wave Technol. Corp., Santa Clara, CA, USA
pp. 691-700

Application of optoelectronic techniques to high speed testing (PDF)

E. Sokolowska , Ecole Polytech., Montreal, Que., Canada
B. Kaminska , Ecole Polytech., Montreal, Que., Canada
pp. 710-719

Back annotation of physical defects into gate-level, realistic faults in digital ICs (PDF)

M. Calha , INESC, Lisbon, Portugal
M. Santos , INESC, Lisbon, Portugal
F. Goncalves , INESC, Lisbon, Portugal
I. Teixeira , INESC, Lisbon, Portugal
J.P. Teixeira , INESC, Lisbon, Portugal
pp. 720-728

Simulation results of an efficient defect analysis procedure (PDF)

O. Stern , Inst. of Comput. Structures, Siegen Univ., Germany
H.-J. Wunderlich , Inst. of Comput. Structures, Siegen Univ., Germany
pp. 729-738

The effect on quality of non-uniform fault coverage and fault probability (PDF)

P.C. Maxwell , Integrated Circuit Bus. Div., Hewlett-Packard Co., USA
R.C. Aitken , Integrated Circuit Bus. Div., Hewlett-Packard Co., USA
pp. 739-746

Application of joint time-frequency analysis in mixed signal testing (PDF)

F. Bouwman , Philips Res. Lab., Eindhoven, Netherlands
T. Zwemstra , Philips Res. Lab., Eindhoven, Netherlands
S. Hartanato , Philips Res. Lab., Eindhoven, Netherlands
K. Baker , Philips Res. Lab., Eindhoven, Netherlands
pp. 747-756

Digitizer error extraction in the nonlinearity test (PDF)

L.S.L. Hsieh , AT&T Bell Labs., Allentown, PA, USA
S.P. Kumar , AT&T Bell Labs., Allentown, PA, USA
pp. 757-762

An improved method of ADC jitter measurement (PDF)

Y. Langard , Thomson-CSF, Orsay, France
J.-L. Balat , Thomson-CSF, Orsay, France
J. Durand , Thomson-CSF, Orsay, France
pp. 763-770

An on-line data collection and analysis system for VLSI devices at wafer probe and final test (PDF)

G.W. Papadeas , Digital Equipment Corp., Hudson, MA, USA
D. Gauthier , Digital Equipment Corp., Hudson, MA, USA
pp. 771-780

Test station workcell controller and resource relationship design (PDF)

S.A. Erjavic , VLSI Technol. Inc., San Jose, CA, USA
pp. 781-792

Calculating error of measurement on high speed microprocessor test (PDF)

T. Comard , Digital Equipment Corp., Hudson, MA, USA
M. Joshi , Digital Equipment Corp., Hudson, MA, USA
D.A. Morin , Digital Equipment Corp., Hudson, MA, USA
K. Sprague , Digital Equipment Corp., Hudson, MA, USA
pp. 793-801

NAND trees accurately diagnose board-level pin faults (PDF)

G.D. Robinson , GenRad Inc., Concord, MA, USA
pp. 811-816

Non-volatile programmable devices and in-circuit test (PDF)

D.W. Raymond , Teradyne Inc., USA
D. Haigh , Teradyne Inc., USA
R. Bodick , Teradyne Inc., USA
B. Ryan , Teradyne Inc., USA
D. McCombs , Teradyne Inc., USA
pp. 817-823

Improving software testability with assertion insertion (PDF)

Hwei Yin , Dept. of Comput. Sci., Colorado State Univ., Fort Collins, CO, USA
J.M. Bieman , Dept. of Comput. Sci., Colorado State Univ., Fort Collins, CO, USA
pp. 831-839

Sleuth : a domain based testing tool (PDF)

A. Von Mayrhauser , Dept. of Comput. Sci., Colorado State Univ., Fort Collins, CO, USA
pp. 840-849

Efficient O(/spl radic/n) BIST algorithms for DDNPS faults in dual port memories (PDF)

A.A. Amin , King Fahd Univ. of Pet. & Miner., Dhahran, Saudi Arabia
M.Y. Osman , King Fahd Univ. of Pet. & Miner., Dhahran, Saudi Arabia
R.E. Abdel-Aal , King Fahd Univ. of Pet. & Miner., Dhahran, Saudi Arabia
H. Al-Muhtaseb , King Fahd Univ. of Pet. & Miner., Dhahran, Saudi Arabia
pp. 850-859

Transparent memory testing for pattern sensitive faults (PDF)

M.G. Karpovsky , Coll. of Eng., Boston Univ., MA, USA
pp. 860-869

Concurrent engineering with DFT in the digital system: a parallel process (PDF)

R. Sanchez , Hughes Aircraft Co., Los Angeles, CA, USA
pp. 879-886

Do you practice safe test? What we found out about your habits (PDF)

C.A. Dean , AT&T Bell Labs., Merrimack Valley, MA, USA
pp. 887-892

Control strategies for chip-based DFT/BIST hardware (PDF)

D. Mukherjee , Dept. of Electr. Eng.-Syst., Univ. of Southern California, Los Angeles, CA, USA
M. Pedram , Dept. of Electr. Eng.-Syst., Univ. of Southern California, Los Angeles, CA, USA
M. Breuer , Dept. of Electr. Eng.-Syst., Univ. of Southern California, Los Angeles, CA, USA
pp. 893-902

Testing two generations of HDTV decoders-the impact of boundary scan test (PDF)

L. Eerenstein , Philips Electron. Design & Tools, Eindhoven, Netherlands
pp. 911-918

Structure and metrology for a single-wire analog testability bus (PDF)

Yunsheng Lu , Dept. of Electr. & Comput. Eng., Colorado Univ., Colorado Springs, CO, USA
pp. 919-928

Fixed-biased pseudorandom built-in self-test for random pattern resistant circuits (PDF)

M.F. Ashaibi , Dept. of Electr. & Comput. Eng., Wisconsin Univ., Madison, WI, USA
C.R. Kime , Dept. of Electr. & Comput. Eng., Wisconsin Univ., Madison, WI, USA
pp. 929-938

Configuring flip-flops to BIST registers (PDF)

A.P. Stroele , Inst. of Comput. Design & Fault Tolerance, Karlsruhe Univ., Germany
pp. 939-948

Making the circular self-test path technique effective for real circuits (PDF)

F. Corno , Dipartimento di Autom. e Inf., Politecnico di Torino, Italy
P. Prinetto , Dipartimento di Autom. e Inf., Politecnico di Torino, Italy
M. Sonza Reorda , Dipartimento di Autom. e Inf., Politecnico di Torino, Italy
pp. 949-957

Behavioral test generation using mixed integer nonlinear programming (PDF)

R.S. Ramchandani , Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
D.E. Thomas , Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
pp. 958-967

B-algorithm: a behavioral test generation algorithm (PDF)

Chang Hyun Cho , Micro Device Bus., Samsung Electron. Co., Bunchun, South Korea
pp. 968-979

Full symbolic ATPG for large circuits (PDF)

G. Cabodi , Politecnico di Torino, Italy
P. Camurati , Politecnico di Torino, Italy
S. Quer , Politecnico di Torino, Italy
pp. 980-988

On synthesizing circuits with implicit testability constraints (PDF)

H. Cox , Cadence Design Syst. Inc., Chelmsford, MA, USA
pp. 989-998

A simulation-based protocol-driven scan test design rule checker (PDF)

E.B. Pitty , Synopsys Inc., Mountain View, CA, USA
D. Martin , Synopsys Inc., Mountain View, CA, USA
H.-K.T. Ma , Synopsys Inc., Mountain View, CA, USA
pp. 999-1006

On achieving complete testability of synchronous sequential circuits with synchronizing sequences (PDF)

I. Pomeranz , Dept. of Electr. & Comput. Eng., Iowa Univ., Iowa City, IA, USA
S.M. Reddy , Dept. of Electr. & Comput. Eng., Iowa Univ., Iowa City, IA, USA
pp. 1007-1016

Integration of design, manufacturing and testing (PDF)

W. Maly , Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
pp. 1017

Navigating test access in systems (PDF)

L. Whetsel , Texas Instrum., USA
pp. 1018

Backplane test bus selection criteria (PDF)

C. Champlin , Motorola Commercial Space, USA
pp. 1021

1149.1 scan control transport levels (PDF)

R. Gage , Sequent Comput. Syst., Beaverton, OR, USA
pp. 1022

Observations on the 1149.x family of standards (PDF)

K.P. Parker , Manuf. Test Div., Hewlett-Packard Co., Loveland, CO, USA
pp. 1023

Optimizing boundary scan in a proprietary environment (PDF)

W. Eklow , Tandem Comput. Inc., Cupertino, CA, USA
pp. 1024

Author index (PDF)

pp. 1031

A practical system for mutation testing: help for the common programmer (PDF)

A.J. Offutt , Dept. of Inf. Syst. & Syst. Eng., George Mason Univ., Fairfax, VA, USA
pp. 824-830

Generating march tests automatically (PDF)

A.J. van de Goor , Dept. of Electr. Eng., Delft Univ. of Technol., Netherlands
B. Smit , Dept. of Electr. Eng., Delft Univ. of Technol., Netherlands
pp. 870-878
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