The Community for Technology Leaders
Proceedings of IEEE International Test Conference - (ITC) (1993)
Baltimore, MD, USA
Oct. 17, 1993 to Oct. 21, 1993
ISBN: 0-7803-1430-1
TABLE OF CONTENTS

A comparison of defect models for fault location with Iddq measurements (PDF)

R.C. Aitken , Hewlett-Packard Co., Santa Clara, CA, USA
pp. 1051-1060

Novel test pattern generators for pseudo-exhaustive testing (PDF)

R. Srinivasan , Dept. of Electr. Eng.-Syst., Univ. of Southern California, Los Angeles, CA, USA
S.K. Gupta , Dept. of Electr. Eng.-Syst., Univ. of Southern California, Los Angeles, CA, USA
M.A. Breuer , Dept. of Electr. Eng.-Syst., Univ. of Southern California, Los Angeles, CA, USA
pp. 1041-1050

Calculation of multiple sets of weights for weighted random testing (PDF)

M. Bershteyn , Mitsubishi Electric Res. Lab., Inc., Sunnyvale, CA, USA
pp. 1031-1040

Generation of optimized single distributions of weights for random built-in self-test (PDF)

M.A. Miranda , Integrated Syst. Lab., Univ. Politecnica de Madrid, Spain
C.A. Lopez-Barrio , Integrated Syst. Lab., Univ. Politecnica de Madrid, Spain
pp. 1023-1030

Inhomogeneous cellular automata for weighted random pattern generation (PDF)

D.J. Neebel , Dept. of Electr. & Comput. Eng., Wisconsin Univ., Madison, WI, USA
C.R. Kime , Dept. of Electr. & Comput. Eng., Wisconsin Univ., Madison, WI, USA
pp. 1013-1022

On selecting flip-flops for partial reset (PDF)

M. Abramovici , AT&T Bell Lab., Naperville, IL, USA
P.S. Parikh , AT&T Bell Lab., Naperville, IL, USA
pp. 1008-1012

A learning-based method to match a test pattern generator to a circuit-under-test (PDF)

I. Pomeranz , Dept. of Electr. & Comput. Eng. Iowa Univ., Iowa City, IA, USA
S.M. Reddy , Dept. of Electr. & Comput. Eng. Iowa Univ., Iowa City, IA, USA
pp. 998-1007

Multiconfiguration technique to reduce test duration for sequential circuits (PDF)

Y. Bertrand , Lab. d'Inf., Univ. de Montpellier II, France
F. Bancel , Lab. d'Inf., Univ. de Montpellier II, France
M. Renovell , Lab. d'Inf., Univ. de Montpellier II, France
pp. 989-997

A serial scan test vector compression methodology (PDF)

C. Su , Dept. of Electr. Eng., Nat. Central Univ., Chung-Li, Taiwan
K. Hwang , Dept. of Electr. Eng., Nat. Central Univ., Chung-Li, Taiwan
pp. 981-988

DELTEST: Deterministic test generation for gate delay faults (PDF)

U. Mahlstedt , Inst. fur Theor. Elektrotechnik, Hannover Univ., Germany
pp. 972-980

Delay testing for non-robust untestable circuits (PDF)

K.-T. Cheng , AT&T Bell Lab., Murray Hill, NJ, USA
H.-C. Chen , AT&T Bell Lab., Murray Hill, NJ, USA
pp. 954-961

MixTest: A mixed-signal extension to a digital test system (PDF)

R. Mehtani , Philips Res. Lab., Eindhoven, Netherlands
B. Atzema , Philips Res. Lab., Eindhoven, Netherlands
M. De Jonghe , Philips Res. Lab., Eindhoven, Netherlands
R. Morren , Philips Res. Lab., Eindhoven, Netherlands
G. Seuren , Philips Res. Lab., Eindhoven, Netherlands
T. Zwemstra , Philips Res. Lab., Eindhoven, Netherlands
pp. 945-953

Terminating transmission lines in the test environment (PDF)

R.F. Herlein , Schlumberger Technol., San Jose, CA, USA
pp. 936-944

CAD driven high precision E-beam positioning (PDF)

K. Kwang , Advantest America, Inc., Santa Clara, CA, USA
H. Wang , Advantest America, Inc., Santa Clara, CA, USA
A. Hu , Advantest America, Inc., Santa Clara, CA, USA
pp. 928-935

High speed sampling capability for a VLSI mixed signal tester (PDF)

P. Sakamoto , Megatest Corp., San Jose, CA, USA
T. Chiu , Megatest Corp., San Jose, CA, USA
pp. 918-927

Knowledge based testing (PDF)

H. Kumar , VLSI Technol., Inc., San Jose, CA, USA
S. Erjavic , VLSI Technol., Inc., San Jose, CA, USA
pp. 910-917

Testable programmable digital clock pulse control elements (PDF)

K.D. Wagner , Synopsys, Inc., Mountain View, CA, USA
pp. 902-909

Differential virtual instrumentation with continuously variable scale (PDF)

B.J. Dinteman , Credence Syst. Corp., Fremont, CA, USA
P. Botsford , Credence Syst. Corp., Fremont, CA, USA
pp. 893-901

Simulation of non-classical faults on the gate level - The fault simulator COMSIM (PDF)

U. Mahlstedt , Inst. fur Theor. Elektrotechnik, Hannover Univ., Germany
J. Alt , Inst. fur Theor. Elektrotechnik, Hannover Univ., Germany
pp. 883-892

On accurate modeling and efficient simulation of CMOS opens (PDF)

C. Di , Dept. of EE, Eindhoven Univ. of Technol., Netherlands
J.A.G. Jess , Dept. of EE, Eindhoven Univ. of Technol., Netherlands
pp. 875-882

Analysis of dynamic effects of resistive bridging faults in CMOS and BiCMOS digital ICs (PDF)

M. Favalli , DEIS, Bologna Univ., Italy
M. Dalpasso , DEIS, Bologna Univ., Italy
P. Olivo , DEIS, Bologna Univ., Italy
B. Ricco , DEIS, Bologna Univ., Italy
pp. 865-874

Efficient testing of software modifications (PDF)

A. von Mayrhauser , Colorado State Univ., CO, USA
K. Olender , Colorado State Univ., CO, USA
pp. 859-864

Automated testing of open software standards (PDF)

J.F. Leathrum , Electr. & Comput. Eng., Clemson Univ., SC, USA
K.A. Liburdy , Electr. & Comput. Eng., Clemson Univ., SC, USA
pp. 854-858

Mutation-based testing of concurrent programs (PDF)

R. Carver , Dept. of Comput. Sci., George Mason Univ., Fairfax, VA, USA
pp. 845-853

"In system" transparent autodiagnostics of RAMs (PDF)

J. Sosnowski , Inst. of Comput. Sci., Warsaw Univ. of Technol., Poland
pp. 835-844

Fault location algorithms for repairable embedded RAMs (PDF)

R.p. Treuer , Dept. of Electr. Eng., McGill Univ., Montreal, Que., Canada
V.K. Agarwal , Dept. of Electr. Eng., McGill Univ., Montreal, Que., Canada
pp. 825-834

Development of a fault model and test algorithms for embedded DRAMs (PDF)

M. Sachdev , Philips Res. Lab., Eindhoven, Netherlands
M. Verstraelen , Philips Res. Lab., Eindhoven, Netherlands
pp. 815-824

A BIST scheme for an SNR test of a sigma-delta ADC (PDF)

M.F. Toner , Dept. of Electr. Eng., McGill Univ., Montreal, Que., Canada
pp. 805-814

Design for testability of a modular, mixed signal family of VLSI devices (PDF)

E. Flaherty , Texas Instrum. Inc., Stafford, TX, USA
A. Allan , Texas Instrum. Inc., Stafford, TX, USA
pp. 797-804

A built-in self-test for ADC and DAC in a single-chip speech CODEC (PDF)

E. Teraoka , Mitsubishi Electr. Corp., Hyogo, Japan
T. Kengaku , Mitsubishi Electr. Corp., Hyogo, Japan
I. Yasui , Mitsubishi Electr. Corp., Hyogo, Japan
K. Ishikawa , Mitsubishi Electr. Corp., Hyogo, Japan
T. Matsuo , Mitsubishi Electr. Corp., Hyogo, Japan
H. Wakada , Mitsubishi Electr. Corp., Hyogo, Japan
N. Sakashita , Mitsubishi Electr. Corp., Hyogo, Japan
Y. Shimazu , Mitsubishi Electr. Corp., Hyogo, Japan
T. Tokuda , Mitsubishi Electr. Corp., Hyogo, Japan
pp. 791-796

VINCI: Secure test of a VLSI high-speed encryption system (PDF)

H. Bonnenberg , Integrated Syst. Lab., Swiss Federal Inst. of Technol., Zurich, Switzerland
A. Curiger , Integrated Syst. Lab., Swiss Federal Inst. of Technol., Zurich, Switzerland
N. Felber , Integrated Syst. Lab., Swiss Federal Inst. of Technol., Zurich, Switzerland
H. Kaeslin , Integrated Syst. Lab., Swiss Federal Inst. of Technol., Zurich, Switzerland
R. ZImmermann , Integrated Syst. Lab., Swiss Federal Inst. of Technol., Zurich, Switzerland
W. Fichtner , Integrated Syst. Lab., Swiss Federal Inst. of Technol., Zurich, Switzerland
pp. 782-790

Testability features of the SuperSPARC microprocessor (PDF)

R. Patel , Sun Microsyst. Inc., Mountain View, CA, USA
K. Yarlagadda , Sun Microsyst. Inc., Mountain View, CA, USA
pp. 773-781

Test features of the HP PA7100LC processor (PDF)

D.D. Josephson , Hewlett Packard Co., Ft. Collins, CO, USA
D.J. Dixon , Hewlett Packard Co., Ft. Collins, CO, USA
B.J. Arnold , Hewlett Packard Co., Ft. Collins, CO, USA
pp. 764-772

A synthesis approach to design for testability (PDF)

S. Kanjilal , Dept. of Comput. Sci., Rutgers Univ., New Brunswick, NJ, USA
pp. 754-763

A conditional resource sharing method for behavioral synthesis of highly testable data paths (PDF)

T.-C. Lee , Dept. of Electr. Eng., Princeton Univ., NJ, USA
N.K. Jha , Dept. of Electr. Eng., Princeton Univ., NJ, USA
W.H. Wolf , Dept. of Electr. Eng., Princeton Univ., NJ, USA
pp. 744-753

Synthesizing for scan dependence in built-in self-testable designs (PDF)

L.J. Avra , Dept. of Electr. Eng. & Comput. Sci., Stanford Univ., CA, USA
E.J. McCluskey , Dept. of Electr. Eng. & Comput. Sci., Stanford Univ., CA, USA
pp. 734-743

Generation of compact delay tests by multiple path activation (PDF)

S. Bose , AT&T Bell Lab., Murray Hill, NJ, USA
P. Agrawal , AT&T Bell Lab., Murray Hill, NJ, USA
V. Agrawal , AT&T Bell Lab., Murray Hill, NJ, USA
pp. 714-723

An implicit delay fault simulation method with approximate detection threshold calculation (PDF)

D. Dumas , Lab. d'Inf. de Robotique, UMR CNRS, Montpellier, France
P. Girard , Lab. d'Inf. de Robotique, UMR CNRS, Montpellier, France
C. Landrault , Lab. d'Inf. de Robotique, UMR CNRS, Montpellier, France
pp. 705-713

FFT based troubleshooting of 120 dB dynamic range ADC systems (PDF)

D. Ownby , Crystal Semicond. Corp., Austin, TX, USA
H. Bogard , Crystal Semicond. Corp., Austin, TX, USA
pp. 690-696

Fault diagnosis of flash ADC using DNL test (PDF)

A. Charoenrook , Dept. of Electr. Eng., Washington Univ., Seattle, WA, USA
M. Soma , Dept. of Electr. Eng., Washington Univ., Seattle, WA, USA
pp. 680-689

Multiple fault diagnosis in printed circuit boards (PDF)

S.J. Barnfield , Dept. of Eng. Sci., Oxford Univ., UK
pp. 662-671

Analog circuit testing based on sensitivity computation and new circuit modeling (PDF)

N.B. Hamida , Ecole Polytech. de Montreal, Que., Canada
B. Kaminska , Ecole Polytech. de Montreal, Que., Canada
pp. 652-661

A general purpose I/sub DDQ/ measurement circuit (PDF)

K. Wallquist , Dept. of Electr. & Comput. Eng., New Mexico Univ., Albuquerque, NM, USA
pp. 642-651

Built-in current sensor for I/sub DDQ/ test in CMOS (PDF)

C.-W. Hsue , AT&T Bell Lab., Princeton, NJ, USA
C.-J. Lin , AT&T Bell Lab., Princeton, NJ, USA
pp. 635-641

I/sub DD/ pulse response testing on analog and digital CMOS circuits (PDF)

J.S. Beasley , New Mexico State Univ., Las Cruces, NM, USA
H. Ramamurthy , New Mexico State Univ., Las Cruces, NM, USA
J. Ramirez-Angulo , New Mexico State Univ., Las Cruces, NM, USA
pp. 626-634

Switch-level ATPG using constraint-guided line justification (PDF)

E.S. Park , Electron. & Telecommun. Res. Inst., Daejon, South Korea
pp. 616-625

CHEETA: Composition of hierarchical sequential tests using ATKET (PDF)

P. Vishakantaiah , Comput. Eng. Res. Center, Texas Univ., Austin, TX, USA
J.A. Abraham , Comput. Eng. Res. Center, Texas Univ., Austin, TX, USA
pp. 606-615

Test pattern generation with restrictors (PDF)

M.H. Konijnenburg , Dept. of Electr. Eng., Delft Univ. of Technol., Netherlands
pp. 598-605

Quality and single-stuck faults (PDF)

E.J. McCluskey , Dept. of Electr. Eng. & Comput. Sci., Stanford Univ., CA, USA
pp. 597

Quality testing requires quality thinking (PDF)

J.M. Soden , Sandia Nat. Lab., Albuquerque, NM, USA
pp. 596

Let's grade all the faults (PDF)

P.C. Maxwell , Hewlett-Packard Co., Santa Clara, CA, USA
pp. 595

Dos and Don'ts in computing fault coverage (PDF)

M. Abramovici , AT&T Bell Lab., Naperville, IL, USA
pp. 594

Practical considerations for mixed-signal test bus (PDF)

N.-C. Lee , Philips Electron. North America Corp., Briarcliff Manor, NY, USA
pp. 591-592

Integrating electrical test into final assembly (PDF)

H. Littlebury , Motorola Logic & Analog Technol. Group, Tempe, AZ, USA
R. Brueckner , Motorola Logic & Analog Technol. Group, Tempe, AZ, USA
pp. 585-589

Catch the ground bounce before it hits your system (PDF)

E. Kurzweil , BULL, Massy, France
M. Lallement , BULL, Massy, France
R. Blanc , BULL, Massy, France
R. Pasquinelli , BULL, Massy, France
pp. 574-584

Fault coverage of DC parametric tests for embedded analog amplifiers (PDF)

M. Soma , Dept. of Electr. Eng., Washington Univ., Seattle, WA, USA
pp. 566-573

Timing analyzer for embedded testing (PDF)

A. Frisch , Tektronix, Inc., Beaverton, OR, USA
T. Almy , Tektronix, Inc., Beaverton, OR, USA
pp. 552-555

BIST for 1149.1-compatible boards: A low-cost and maximum-flexibility solution (PDF)

J.M.M. Ferreira , INESC, Porto, Portugal
M.G. Gericota , INESC, Porto, Portugal
J.L. Ramalho , INESC, Porto, Portugal
G.R. Alves , INESC, Porto, Portugal
pp. 536-543

IEEE P1149.5 to 1149.1 data and protocol conversion (PDF)

C. Poirier , Nat. Semicond., South Portland, ME, USA
pp. 527-535

PSBIST: A partial-scan based built-in self-test scheme (PDF)

C.-J. Lin , AT&T Bell Lab., Princeton, NJ, USA
Y. Zorian , AT&T Bell Lab., Princeton, NJ, USA
S. Bhawmik , AT&T Bell Lab., Princeton, NJ, USA
pp. 507-516

Partial scan at the register-transfer level (PDF)

J. Steensma , IMEC, Leuven, Belgium
F. Catthoor , IMEC, Leuven, Belgium
H. De Man , IMEC, Leuven, Belgium
pp. 488-497

A flexible approach to data collection for component test systems (PDF)

J. Mosley , Schlumberger Technol., San Jose, CA, USA
pp. 461-470

Minimizing test time by exploiting parallelism in macro test (PDF)

H. Bouwmeester , Philips Res. Lab., Eindhoven, Netherlands
S. Oostdijk , Philips Res. Lab., Eindhoven, Netherlands
F. Bouwmann , Philips Res. Lab., Eindhoven, Netherlands
R. Stans , Philips Res. Lab., Eindhoven, Netherlands
pp. 451-460

Keep alive-A new requirement for high performance /spl mu/processor test (PDF)

R. Garcia , Schlumberter Technol., San Jose, CA, USA
pp. 446-450

Extraction of coupled SPICE models for packages and interconnects (PDF)

S. Diamond , Tektronix Inc., Beaverton, OR, USA
B. Janko , Tektronix Inc., Beaverton, OR, USA
pp. 436-445

Workstation based parallel test generation (PDF)

R.H. Klenke , Virginia Univ., Charlottesville, VA, USA
L. Kaufman , Virginia Univ., Charlottesville, VA, USA
J.H. Aylor , Virginia Univ., Charlottesville, VA, USA
R. Waxman , Virginia Univ., Charlottesville, VA, USA
P. Narayan , Virginia Univ., Charlottesville, VA, USA
pp. 419-428

IEEE 1149 standards - Changing testing, silicon to systems (PDF)

R.E. Tulloss , AT&T Bell Lab., Princeton, NJ, USA
pp. 399-408

IRIDIUM satellite: A large system application of design for testability (PDF)

C. Champlin , Motorola Commercial Space, Chandler, AZ, USA
pp. 392-398

Algorithms for cost optimised test strategy selection (PDF)

C. Dislis , Dept. of Electr. Eng. & Electron., Brunel Univ., Uxbridge, UK
pp. 383-391

Design-for-test techniques utilized in an avionics computer MCM (PDF)

R.J. Wagner , Rockwell Int. Corp., Cedar Rapids, IA, USA
J.A. Jorgenson , Rockwell Int. Corp., Cedar Rapids, IA, USA
pp. 373-382

MCM foundry test methodology and implementation (PDF)

L. Roszel , Texas Instrum., Inc., Dallas, TX, USA
pp. 369-372

A test methodology for VLSI chips on silicon (PDF)

T. Storey , IBM Corp., Manassas, VA, USA
pp. 359-368

BIST for embedded static RAMs with coverage calculation (PDF)

J. van Sas , Alcatel Bell Telephone, Antwerpen, Belgium
G. Van Wauwe , Alcatel Bell Telephone, Antwerpen, Belgium
E. Huyskens , Alcatel Bell Telephone, Antwerpen, Belgium
D. Rabaey , Alcatel Bell Telephone, Antwerpen, Belgium
pp. 339-348

Structured CBIST in ASICS (PDF)

R. Gage , Sequent Comput. Syst., Beaverton, OR, USA
pp. 332-338

Control and observation of analog nodes in mixed-signal boards (PDF)

J.S. Matos , INESC, Portugal
A.C. Leao , INESC, Portugal
J.C. Ferreira , INESC, Portugal
pp. 323-331

Structure and metrology for an analog testability bus (PDF)

K.P. Parker , Hewlett-Packard Co., Loveland, CO, USA
J.E. McDermid , Hewlett-Packard Co., Loveland, CO, USA
S. Oresjo , Hewlett-Packard Co., Loveland, CO, USA
pp. 309-317

Very-low-voltage testing for weak CMOS logic ICs (PDF)

H. Hao , Dept. of Electr. Eng. & Comput. Sci., Stanford Univ., CA, USA
E.J. McCluskey , Dept. of Electr. Eng. & Comput. Sci., Stanford Univ., CA, USA
pp. 275-284

The evolving role of testing in open systems standards (PDF)

J.F. Leathrum , Dept. of Electr. & Comput. Eng., Clemson Univ., SC, USA
K.A. Liburdy , Dept. of Electr. & Comput. Eng., Clemson Univ., SC, USA
pp. 273-274

Software regression testing success story (PDF)

M.A. Long , GenRad, Inc., Concord, MA, USA
pp. 271-272

Cultural evolution in software testing (PDF)

A. Elentukh , Motorola Codex, Mansfield, MA, USA
pp. 270

Scan DFT: Why more can cost less (PDF)

P. Varma , CrossCheck Technol. Inc., San Jose, CA, USA
pp. 267

Known good die for MCMs: Enabling technologies (PDF)

D.C. Keezer , Dept. of Electr. Eng., Univ. of South Florida, Tampa, FL, USA
pp. 266

Benefits of boundary-scan to in-circuit test (PDF)

D.A. Greene , NCR Corp., West Columbia, SC, USA
pp. 263

A method for delay fault self-testing of macrocells (PDF)

H.N. Scholz , AT&T Bell Lab., Allentown, PA, USA
D.R. Aadsen , AT&T Bell Lab., Allentown, PA, USA
pp. 253-261

Delay testing using a matrix of accessible storage elements (PDF)

P. Varma , CrossCheck Technol. Inc., San Jose, CA, USA
T. Gheewala , CrossCheck Technol. Inc., San Jose, CA, USA
pp. 243-252

BIST and delay fault detection (PDF)

S. Pilarski , Sch. of Comput. Sci., Simon Fraser Univ., Burnaby, BC, Canada
A. Pierzynska , Sch. of Comput. Sci., Simon Fraser Univ., Burnaby, BC, Canada
pp. 236-242

The economics of guardband placement (PDF)

R.H. Williams , Dept. of Electr. & Comput. Eng. New Mexico Univ., Albuquerque, NM, USA
C.F. Hawkins , Dept. of Electr. & Comput. Eng. New Mexico Univ., Albuquerque, NM, USA
pp. 218-225

Certification trails and software design for testability (PDF)

G.F. Sullivan , Dept. of Comput. Sci., Johns Hopkins Univ., Baltimore, MD, USA
D.S. Wilson , Dept. of Comput. Sci., Johns Hopkins Univ., Baltimore, MD, USA
G.M. Masson , Dept. of Comput. Sci., Johns Hopkins Univ., Baltimore, MD, USA
pp. 200-209

On the design for testability of communication software (PDF)

S.T. Chanson , Dept. of Comput. Sci., British Columbia Univ., Vancouver, BC, Canada
A.A.F. Loureiro , Dept. of Comput. Sci., British Columbia Univ., Vancouver, BC, Canada
S.T. Vuong , Dept. of Comput. Sci., British Columbia Univ., Vancouver, BC, Canada
pp. 190-199

On the evaluation of software inspections and tests (PDF)

J.K. Chaar , IBM T.J. Watson Res. Center, Yorktown Heights, NY, USA
M.J. Halliday , IBM T.J. Watson Res. Center, Yorktown Heights, NY, USA
I.S. Bhandari , IBM T.J. Watson Res. Center, Yorktown Heights, NY, USA
R. Chillarege , IBM T.J. Watson Res. Center, Yorktown Heights, NY, USA
pp. 180-189

Using boundary scan test to test random access memory clusters (PDF)

M. Muris , Philips Electron. Design & Tools, Eindhoven, Netherlands
A. Biewenga , Philips Electron. Design & Tools, Eindhoven, Netherlands
pp. 174-179

Utilizing boundary scan to implement BIST (PDF)

T. Langford , NCR, Wichita, KS, USA
pp. 167-173

Technology-independent boundary scan synthesis (technology and physical issues) (PDF)

M.F. Robinson , Synopsys Inc., Mountain View, CA, USA
F. Mailhot , Synopsys Inc., Mountain View, CA, USA
pp. 157-166

Visualizing test information: A novel approach for improving testability (PDF)

J. Moorman , Dept. of Comput. Sci., Illinois Univ., Urbana, IL, USA
pp. 149-156

Automatic test plan generation for analog and mixed signal integrated circuits using partial activation and high level simulation (PDF)

N. Ravindranath , Texas Instrum. Pvt. Ltd., Bangalore, India
G.N. Nandakumar , Texas Instrum. Pvt. Ltd., Bangalore, India
K. Srinivasa Rao , Texas Instrum. Pvt. Ltd., Bangalore, India
pp. 139-148

Parameter monitoring: Advantages and pitfalls (PDF)

M.M.A. van Rosmalen , Philips Res. Lab., Eindhoven, Netherlands
K. Baker , Philips Res. Lab., Eindhoven, Netherlands
E.M.J.G. Bruls , Philips Res. Lab., Eindhoven, Netherlands
pp. 115-124

Application of statistical techniques to critical system parameters (PDF)

R. Boyle , Tandem Comput. Inc., Cupertino, CA, USA
J. Donovan , Tandem Comput. Inc., Cupertino, CA, USA
E. Hnatek , Tandem Comput. Inc., Cupertino, CA, USA
A. Ijaz , Tandem Comput. Inc., Cupertino, CA, USA
pp. 108-114

Automated wafer lot approval: A statistically based implementation (PDF)

K.A. Milne , Hewlett Packard Co., Ft. Collins, CO, USA
pp. 92-98

CMOS bridges and resistive transistor faults: IDDQ versus delay effects (PDF)

H.T. Vierhaus , German Nat. Res. Center for Comput. Sci., Syst. Design Technol. Inst., St. Augustin, Germany
W. Meyer , German Nat. Res. Center for Comput. Sci., Syst. Design Technol. Inst., St. Augustin, Germany
U. Glaser , German Nat. Res. Center for Comput. Sci., Syst. Design Technol. Inst., St. Augustin, Germany
pp. 83-91

Test generation with high coverages for quiescent current test of bridging faults in combinational circuits (PDF)

E. Isern , Dept. d'Enginyeria Electron., Univ. Politecnica de Catalunya, Barcelona, Spain
J. Figueras , Dept. d'Enginyeria Electron., Univ. Politecnica de Catalunya, Barcelona, Spain
pp. 73-82

Biased voting: A method for simulating CMOS bridging faults in the presence of variable gate logic thresholds (PDF)

P.C. Maxwell , Hewlett-Packard Co., Santa Clara, CA, USA
R.C. Aitken , Hewlett-Packard Co., Santa Clara, CA, USA
pp. 63-72

Fast and accurate CMOS bridging fault simulation (PDF)

J. Rearick , Hewlett-Packard, Ft. Collins, CO, USA
pp. 54-62

System level interconnect test in a tristate environment (PDF)

F.W. Angelotti , IBM Application Bus. Syst. Div., Rochester, MN, USA
W.A. Britson , IBM Application Bus. Syst. Div., Rochester, MN, USA
K.T. Kaliszewski , IBM Application Bus. Syst. Div., Rochester, MN, USA
S.M. Douskey , IBM Application Bus. Syst. Div., Rochester, MN, USA
pp. 45-53
78 ms
(Ver 3.3 (11022016))