The Community for Technology Leaders
1990 International Test Conference (1990)
Washington, DC, USA
Sept. 10, 1990 to Sept. 14, 1990
ISBN: 0-8186-9064-X
TABLE OF CONTENTS

A method to calculate necessary assignments in algorithmic test pattern generation (PDF)

J. Rajski , Dept. of Electr. Eng., McGill Univ., Montreal, Que., Canada
H. Cox , Dept. of Electr. Eng., McGill Univ., Montreal, Que., Canada
pp. 25-34

Global cost functions for test generation (PDF)

M. Abramovici , AT&T Bell Lab., Naperville, IL, USA
D.T. Miller , AT&T Bell Lab., Naperville, IL, USA
pp. 35-43

ATPG for ultra-large structured designs (PDF)

J.A. Waicukauski , Mentor Graphics Corp., Beaverton, OR, USA
P.A. Shupe , Mentor Graphics Corp., Beaverton, OR, USA
D.J. Giramma , Mentor Graphics Corp., Beaverton, OR, USA
A. Matin , Mentor Graphics Corp., Beaverton, OR, USA
pp. 44-51

A diagnostic test pattern generation algorithm (PDF)

P. Camurati , Dipartimento di Autom. & Inf., Politecnico di Torino, Turin, Italy
D. Medina , Dipartimento di Autom. & Inf., Politecnico di Torino, Turin, Italy
P. Prinetto , Dipartimento di Autom. & Inf., Politecnico di Torino, Turin, Italy
M. Sonza Reorda , Dipartimento di Autom. & Inf., Politecnico di Torino, Turin, Italy
pp. 52-58

Test features of the MC145472 ISDN U-transceivers (PDF)

L. Bonet , Motorola Inc., Austin, TX, USA
J. Ganger , Motorola Inc., Austin, TX, USA
J. Girardeau , Motorola Inc., Austin, TX, USA
C. Greaves , Motorola Inc., Austin, TX, USA
M. Pendleton , Motorola Inc., Austin, TX, USA
D. Yatim , Motorola Inc., Austin, TX, USA
pp. 68-79

ATE-based functional ISDN testing (PDF)

K. Lanier , LTX Corp., Westwood, MA, USA
pp. 86-94

ASSIST (Allied Signal's Standardized Integrated Scan Test) (PDF)

G. Sapp , Allied Signal Aerosp. Co., Columbia, MD, USA
pp. 95-102

Innovative techniques for improved testability (PDF)

E.F. Sarkany , IBM Corp., Endicott, NY, USA
R.F. Lusch , IBM Corp., Endicott, NY, USA
pp. 103-108

Testability implemented in the VAX 6000 model 400 (PDF)

J. Sweeney , Digital Equipment Corp., Andover, MA, USA
pp. 109-114

Scan based guided probe technology delivers Cyclone to the market (PDF)

C.J. Choi , Tandem Comput. Inc., Cupertino, CA, USA
pp. 115-119

Optimal placement of IEEE 1149.1 test port and boundary scan resources for wafer scale integration (PDF)

D.L. Landis , Dept. of Electr. Eng., Univ. of South Florida, Tampa, FL, USA
P. Singh , Dept. of Electr. Eng., Univ. of South Florida, Tampa, FL, USA
pp. 120-126

Event qualification: a gateway to at-speed system testing (PDF)

L. Whetsel , Texas Instrum. Inc., Plano, TX, USA
pp. 135-141

Mixed-mode ATPG under input constraints (PDF)

C.T. Glover , Motorola Inc., Austin, TX, USA
pp. 142-151

Multiple path sensitization for hierarchical circuit testing (PDF)

Chau-Chin Su , Dept. of Electr. Eng., Nat. Central Univ., Chung-Li, Taiwan
pp. 152-161

Functional test generation for finite state machines (PDF)

K.-T. Cheng , AT&T Bell Lab., Murray Hill, NJ, USA
J.-Y. Jou , AT&T Bell Lab., Murray Hill, NJ, USA
pp. 162-168

A comprehensive approach for modeling and testing analog and mixed-signal devices (PDF)

T.M. Souders , Nat. Inst. of Stand. & Technol., Gaithersburg, MD, USA
G.N. Stenbakken , Nat. Inst. of Stand. & Technol., Gaithersburg, MD, USA
pp. 169-176

From specification to measurement: the bottleneck in analog industrial testing (PDF)

R.J. van Rijsinge , Philips Components, Nijmegen, Netherlands
A.A.R.M. Haggenburg , Philips Components, Nijmegen, Netherlands
C. de Vries , Philips Components, Nijmegen, Netherlands
pp. 177-182

A design-for-test methodology for active analog filters (PDF)

M. Soma , Design & Test & Reliability Lab., Seattle, WA, USA
pp. 183-192

Stress profile derivation-an empirical approach (PDF)

A.C. Walker , IBM Corp., San Jose, CA, USA
pp. 193-207

Time margin issues in disk drive testing (PDF)

D. Gill , Act Technol. Corp., Anaheim, CA, USA
pp. 214-221

A language for describing boundary-scan devices (PDF)

K.P. Parker , Hewlett-Packard Co., Loveland, CO, USA
S. Oresjo , Hewlett-Packard Co., Loveland, CO, USA
pp. 222-234

Boundary scan test used at board level: moving towards reality (PDF)

F. de Jong , Nederlandse Philips Bedrijven BV, Eindhoven, Netherlands
pp. 235-242

ATPG issues for board designs implementing boundary scan (PDF)

D. Sterba , Texas Instruments, Plano, TX, USA
A. Halliday , Texas Instruments, Plano, TX, USA
D. McClean , Texas Instruments, Plano, TX, USA
pp. 243-251

Why, I/sub DDQ/? (CMOS IC testing) (PDF)

S. McEuen , Ford Microelectron. Inc., Colorado Springs, CO, USA
pp. 252

I/sub DDQ/ testing because 'zero defects isn't enough': a Philips perspective (PDF)

K. Baker , Philips Res. Lab., Eindhoven, Netherlands
B. Verhelst , Philips Res. Lab., Eindhoven, Netherlands
pp. 253-254

Zero defects or zero stuck-at faults-CMOS IC process improvement with I/sub DDQ/ (PDF)

J.M. Soden , Sandia Nat. Lab., Albuquerque, NM, USA
R.R. Fritzemeier , Sandia Nat. Lab., Albuquerque, NM, USA
pp. 255-256

Current testing (PDF)

W. Maly , Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
pp. 257

Concurrent engineering (PDF)

A. Lowenstein , Prospective Computer Analysts Inc., Roslyn, NY, USA
S. Schlosser , Prospective Computer Analysts Inc., Roslyn, NY, USA
G. Winter , Prospective Computer Analysts Inc., Roslyn, NY, USA
pp. 258-259

Obstacles and an approach towards concurrent engineering (PDF)

M.A. Breuer , Dept. of Electr. Eng.-Syst., Univ. of Southern California, Los Angeles, CA, USA
pp. 260-261

QML (qualified manufacturing line): a method of providing high quality integrated circuits (PDF)

N.E. Donlin , US Army Missile Command, Product Assurance Directorate, Redstone Arsenal, AL, USA
pp. 262-263

Test engineers role in QML (PDF)

R.W. Thomas , Rome Air Dev. Center, Griffiss Air Force Base, NY, USA
pp. 264

Testability preserving transformations in multi-level logic synthesis (PDF)

J. Rajski , VLSI Design Lab., McGill Univ., Montreal, Que., Canada
J. Vasudevamurthy , VLSI Design Lab., McGill Univ., Montreal, Que., Canada
pp. 265-273

Sequential logic synthesis for testability using register-transfer level descriptions (PDF)

A. Ghosh , Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
S. Davadas , Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
A.R. Newton , Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
pp. 274-283

Design of integrated circuits fully testable for delay-faults and multifaults (PDF)

S. Devadas , Dept. of Electr. Eng. & Comput. Sci., MIT, Cambridge, MA, USA
pp. 284-293

Functional test and diagnosis: a proposed JTAG sample mode scan tester (PDF)

M.E. Lefebvre , Digital Equipment Corp., Andover, MA, USA
pp. 294-303

Scan test architectures for digital board testers (PDF)

M.L. Fichtenbaum , GenRad Inc, Concord, MA, USA
G.D. Robinson , GenRad Inc, Concord, MA, USA
pp. 304-310

The boundary-scan master: target applications and functional requirements (PDF)

C.W. Yau , AT&T Bell Lab., Princeton, NJ, USA
N. Jarwala , AT&T Bell Lab., Princeton, NJ, USA
pp. 311-315

Testability considerations in the design of the MC68340 Integrated Processor Unit (PDF)

P.E. Bishop , Motorola Inc., Austin, TX, USA
G.L. Giles , Motorola Inc., Austin, TX, USA
S.N. Iyengar , Motorola Inc., Austin, TX, USA
C.T. Glover , Motorola Inc., Austin, TX, USA
W.-o. Law , Motorola Inc., Austin, TX, USA
pp. 337-346

Sequencer Per Pin test system architecture (PDF)

B. West , Schlumberger Technol., San Jose, CA, USA
T. Napier , Schlumberger Technol., San Jose, CA, USA
pp. 355-361

Multiplexing test system channels for data rates above 1 Gb/s (PDF)

D.C. Keezer , Center for Microelectron. Res., Univ. of South Forida, Tampa, FL, USA
pp. 362-368

Design of scan-testable CMOS sequential circuits (PDF)

B.-H. Park , Dept. of Electr. & Comput. Eng., Massachusett Univ., Amherst, MA, USA
P.R. Menon , Dept. of Electr. & Comput. Eng., Massachusett Univ., Amherst, MA, USA
pp. 369-376

An optimization based approach to the partial scan design problem (PDF)

V. Chickermane , Center for Reliable & High Performance Comput., Illinois Univ., Urbana, IL, USA
J.H. Patel , Center for Reliable & High Performance Comput., Illinois Univ., Urbana, IL, USA
pp. 377-386

Arrangement of latches in scan-path design to improve delay fault coverage (PDF)

W. Mao , Dept. of Electr. & Comput. Eng., Colorado Univ., CO, USA
M.D. Ciletti , Dept. of Electr. & Comput. Eng., Colorado Univ., CO, USA
pp. 387-393

An interactive environment for the transparent logic simulation and testing of integrated circuits (PDF)

G.L. Castrodale , Dept. of Electr. Eng., Duke Univ., Durham, NC, USA
A. Dollas , Dept. of Electr. Eng., Duke Univ., Durham, NC, USA
pp. 394-403

ASIC CAD system based on hierarchical design-for-testability (PDF)

M. Emori , Fujitsu Ltd., Kawasaki, Japan
T. Aikyo , Fujitsu Ltd., Kawasaki, Japan
Y. Machida , Fujitsu Ltd., Kawasaki, Japan
J.-i. Shikatani , Fujitsu Ltd., Kawasaki, Japan
pp. 404-409

CMP3F: a high speed fault simulator for the Connection Machine (PDF)

A. Agrawal , Dept. of Comput. Sci., Brown Univ., Providence, RI, USA
pp. 410-416

On the charge sharing problem in CMOS stuck-open fault testing (PDF)

K.-J. Lee , Dept. of Electr. Eng.-Syst., Univ. of Southern California, Los Angeles, CA, USA
M.A. Breuer , Dept. of Electr. Eng.-Syst., Univ. of Southern California, Los Angeles, CA, USA
pp. 417-426

Increased CMOS IC stuck-at fault coverage with reduced I/sub DDQ/ test sets (PDF)

R.R. Fritzemeier , Sandia Nat. Lab., Albuquerque, NM, USA
J.M. Soden , Sandia Nat. Lab., Albuquerque, NM, USA
R.K. Treece , Sandia Nat. Lab., Albuquerque, NM, USA
pp. 427-435

Testing for parametric faults in static CMOS circuits (PDF)

F.J. Ferguson , Dept. of Eng., California Univ., Santa Cruz, CA, USA
M. Taylor , Dept. of Eng., California Univ., Santa Cruz, CA, USA
T. Larrabee , Dept. of Eng., California Univ., Santa Cruz, CA, USA
pp. 436-443

Frequency enhancement of digital VLSI test systems (PDF)

L. Ackner , AT&T Bell Lab., Allentown, PA, USA
M.R. Barber , AT&T Bell Lab., Allentown, PA, USA
pp. 444-451

Critical parameters for high-performance dynamic response measurements (PDF)

D.F. Murray , Tektronix Inc., Beaverton, OR, USA
C.M. Nash , Tektronix Inc., Beaverton, OR, USA
pp. 462-471

Integrating boundary scan test into an ASIC design flow (PDF)

M. Muris , Nederlandse Philips Bedrijven BV, Eindhoven, Netherlands
pp. 472-477

A study of the optimization of DC parametric tests (PDF)

J.M. Chang , AT&T Bell Lab., Allentown, PA, USA
pp. 478-487

Direct access test scheme-design of block and core cells for embedded ASICs (PDF)

V. Immaneni , Intel Corp., Chandler, AZ, USA
S. Raman , Intel Corp., Chandler, AZ, USA
pp. 488-492

Color reproduction test for CCD image sensors (PDF)

H. Kato , Advantest Lab. Ltd., Otaru, Japan
pp. 493-497

A rapid dither algorithm advances A/D converter testing (PDF)

J. Weimer , Eagle Test Systems Inc., Mundelein, IL, USA
K. Baade , Eagle Test Systems Inc., Mundelein, IL, USA
J. Fitzsimmons , Eagle Test Systems Inc., Mundelein, IL, USA
B. Lowe , Eagle Test Systems Inc., Mundelein, IL, USA
pp. 498-507

An advanced test system architecture for synchronous and asynchronous control of mixed signal device testing (PDF)

J. Kurita , Yokogawa-Hewlett-Packard Ltd., Tokyo, Japan
N. Kasuga , Yokogawa-Hewlett-Packard Ltd., Tokyo, Japan
K. Hiwada , Yokogawa-Hewlett-Packard Ltd., Tokyo, Japan
pp. 508-513

An analysis of ATE computational architecture (PDF)

A.R. Taylor , LTX/Trillium, San Jose, CA, USA
pp. 514-519

Hierarchical test assembly for macro based VLSI design (PDF)

J. Leenstra , Inst. for Microelectron. Stuttgart, West Germany
L. Spaanenburg , Inst. for Microelectron. Stuttgart, West Germany
pp. 520-529

enVision: the inside story (PDF)

D. Organ , LTX/Trillium, San Jose, CA, USA
pp. 530-536

Error masking in self-testable circuits (PDF)

A.P. Stroele , Inst. of Comput. Design & Fault Tolerance, Karlsruhe Univ., Germany
H.-J. Wunderlich , Inst. of Comput. Design & Fault Tolerance, Karlsruhe Univ., Germany
pp. 544-552

An architecture for high-speed analog in-circuit testing (PDF)

L. Klein , Teradyne Inc., Boston, MA, USA
J. Bridgeman , Teradyne Inc., Boston, MA, USA
pp. 562-564

Diagnosis for wiring interconnects (PDF)

W.-T. Cheng , ADAS Software Inc., San Jose, CA, USA
pp. 565-571

Interconnect testing of boards with partial boundary scan (PDF)

G.D. Robinson , GenRad Inc., Concord, MA, USA
J.G. Deshayes , GenRad Inc., Concord, MA, USA
pp. 572-581

Towards a standard approach for controlling board-level test functions (PDF)

B.I. Dervisoglu , Hewlett Packard/APOLLO, Chelmsford, MA, USA
pp. 582-590

A new approach to mixed-signal diagnosis (PDF)

R. Rastogi , Cimflex Teknowledge Corp., Pittsburgh, PA, USA
K. Sierzega , Cimflex Teknowledge Corp., Pittsburgh, PA, USA
pp. 591-597

A fourth generation analog incircuit program generator (PDF)

D.T. Crook , Hewlett-Packard Co., Loveland, CO, USA
pp. 605-612

Jitter minimization technique for mixed signal testing (PDF)

Y. Furukawa , Advantest Corp., Saitama, Japan
M. Kimura , Advantest Corp., Saitama, Japan
M. Sugai , Advantest Corp., Saitama, Japan
pp. 613-619

Optimized testing of meshes (PDF)

M. Malek , Dept. of Electr. & Comput. Eng., Texas Univ., Austin, TX, USA
B. Ozden , Dept. of Electr. & Comput. Eng., Texas Univ., Austin, TX, USA
pp. 627-637

Identification of faulty processing elements by space-time compression of test responses (PDF)

M.G. Karpovsky , Dept. of Electr. Comput. & Syst. Eng., Boston Univ., MA, USA
L.B. Levitin , Dept. of Electr. Comput. & Syst. Eng., Boston Univ., MA, USA
F.S. Vainstein , Dept. of Electr. Comput. & Syst. Eng., Boston Univ., MA, USA
pp. 638-647

Failure probability algorithm for test systems to reduce false alarms (PDF)

D.R. Allen , Northrop Corp., Hawthorne, CA, USA
pp. 648-656

A multiple seed linear feedback shift register (PDF)

J. Savir , IBM Corp., Poughkeepsie, NY, USA
W.H. McAnney , IBM Corp., Poughkeepsie, NY, USA
pp. 657-659

A new procedure for weighted random built-in self-test (PDF)

F. Muradali , VLSI Design Lab., McGill Univ., Montreal, Que., Canada
V.K. Agarwal , VLSI Design Lab., McGill Univ., Montreal, Que., Canada
pp. 660-669

Generating pseudo-exhaustive vectors for external testing (PDF)

S. Hellebrand , Inst. of Comput. Design & Fault Tolerance, Karlsruhe Univ., Germany
H.-J. Wunderlich , Inst. of Comput. Design & Fault Tolerance, Karlsruhe Univ., Germany
O.F. Haberl , Inst. of Comput. Design & Fault Tolerance, Karlsruhe Univ., Germany
pp. 670-679

Computer-aided design of pseudoexhaustive BIST for semiregular circuits (PDF)

Chau-Chin Su , Dept. of Electr. Eng., Nat. Central Univ., Chung-Li, Taiwan
pp. 680-689

Fault simulation of logic designs on parallel processors with distributed memory (PDF)

L.M. Huisman , IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA
pp. 690-697

Experimental evaluation of concurrent fault simulation algorithms on scalable, hierarchically defined test cases (PDF)

W.H. Nicholls , Boeing Aerosp. & Electron., Seattle, WA, USA
A.W. Nordsieck , Boeing Aerosp. & Electron., Seattle, WA, USA
pp. 698-705

Parallel pattern fault simulation based on stem faults in combinational circuits (PDF)

O. Song , Dept. of Electr. & Comput. Eng., Massachusetts Univ., Amherst, MA, USA
P.R. Menon , Dept. of Electr. & Comput. Eng., Massachusetts Univ., Amherst, MA, USA
pp. 706-711

Extending binary searches to two and three dimensions (IC testing) (PDF)

R.L. Hickling , Schlumberger Technol., San Jose, CA, USA
pp. 721-725

AC product defect level and yield loss (PDF)

J. Savir , IBM Corp., Poughkeepsie, NY, USA
pp. 726-738

Macro-testability and the VSP (PDF)

R. Mehtani , Philips Res. Lab., Eindhoven, Netherlands
K. Baker , Philips Res. Lab., Eindhoven, Netherlands
C.M. Huizer , Philips Res. Lab., Eindhoven, Netherlands
P.J. Hynes , Philips Res. Lab., Eindhoven, Netherlands
J. van Beers , Philips Res. Lab., Eindhoven, Netherlands
pp. 739-748

Testability features of the 68040 (PDF)

M.G. Gallup , Motorola Inc., Austin, TX, USA
W. Ledbetter , Motorola Inc., Austin, TX, USA
R. McGarity , Motorola Inc., Austin, TX, USA
S. McMahan , Motorola Inc., Austin, TX, USA
K.C. Scheuer , Motorola Inc., Austin, TX, USA
C.G. Shepard , Motorola Inc., Austin, TX, USA
L. Sood , Motorola Inc., Austin, TX, USA
pp. 749-757

Fault grading the Intel 80486 (PDF)

N. Gollakota , Intel Corp., Santa Clara, CA, USA
A. Zaidi , Intel Corp., Santa Clara, CA, USA
pp. 758-761

Cellular automata based self-test for programmable data paths (PDF)

J. van Sas , IMEC Lab., Leuven, Belgium
F. Catthoor , IMEC Lab., Leuven, Belgium
H. De Man , IMEC Lab., Leuven, Belgium
pp. 769-778

Design of signature circuits based on weight distributions of error-correcting codes (PDF)

K. Iwasaki , Hitachi Ltd., Tokyo, Japan
N. Yamaguchi , Hitachi Ltd., Tokyo, Japan
pp. 779-785

Why is less information from logic simulation more useful in fault simulation? (PDF)

S.B. Akers , Massachusetts Univ., Amherst, MA, USA
S. Park , Massachusetts Univ., Amherst, MA, USA
pp. 786-800

The dynamic reduction of fault simulation (PDF)

F. Maamari , Dept. of Electr. Eng., McGill Univ., Montreal, Que., Canada
J. Rajski , Dept. of Electr. Eng., McGill Univ., Montreal, Que., Canada
pp. 801-808

Single-fault fault collapsing analysis in sequential logic circuits (PDF)

J.E. Chen , Inst. of Electron., Nat. Chiao Tung Univ., Hsin-Chu, Taiwan
Chung Len Lee , Inst. of Electron., Nat. Chiao Tung Univ., Hsin-Chu, Taiwan
Wen Zen Shen , Inst. of Electron., Nat. Chiao Tung Univ., Hsin-Chu, Taiwan
pp. 809-814

A BIST scheme using microprogram ROM for large capacity memories (PDF)

H. Koike , NEC Corp., Kanagawa, Japan
T. Takeshima , NEC Corp., Kanagawa, Japan
M. Takada , NEC Corp., Kanagawa, Japan
pp. 815-822

Analysis of failures on memories using expert system techniques (PDF)

T. Viacroze , IBM France, Cestas, France
M. Lequeux , IBM France, Cestas, France
pp. 823-832

A novel built-in self-repair approach to VLSI memory yield enhancement (PDF)

P. Mazumder , Dept. of Electr. Eng. & Comput. Sci., Michigan Univ., Ann Arbor, MI, USA
J.S. Yih , Dept. of Electr. Eng. & Comput. Sci., Michigan Univ., Ann Arbor, MI, USA
pp. 833-841

CMOS bridging fault detection (PDF)

T.M. Storey , Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
W. Maly , Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
pp. 842-851

Bridging faults and their implication to PLAs (PDF)

V. Chandramouli , Ford Microelectron. Inc., Colorado Springs, CO, USA
R.K. Gulati , Ford Microelectron. Inc., Colorado Springs, CO, USA
pp. 852-859

Diagnosing CMOS bridging faults with stuck-at fault dictionaries (PDF)

S.D. Millman , Comput. Syst. Lab., Stanford Univ., CA, USA
E.J. McCluskey , Comput. Syst. Lab., Stanford Univ., CA, USA
pp. 860-870

EEODM: An effective BIST scheme for ROMs (PDF)

Y. Zorian , AT&T Bell Lab., Princeton, NJ, USA
pp. 871-879

Built-in self-test in a 24 bit floating point digital signal processor (PDF)

N. Sakashita , Mitsubishi Electr. Corp., Hyogo, Japan
H. Sawai , Mitsubishi Electr. Corp., Hyogo, Japan
E. Teraoka , Mitsubishi Electr. Corp., Hyogo, Japan
T. Fujiyama , Mitsubishi Electr. Corp., Hyogo, Japan
T. Kengaku , Mitsubishi Electr. Corp., Hyogo, Japan
Y. Shimazu , Mitsubishi Electr. Corp., Hyogo, Japan
T. Tokuda , Mitsubishi Electr. Corp., Hyogo, Japan
pp. 880-885

Complete self-test architecture for a coprocessor (cryptography) (PDF)

T.M. Schwair , Siemens AG, Munich, Germany
H.C. Ritter , Siemens AG, Munich, Germany
pp. 886-890

High-speed fixture interconnects for mixed-signal IC testing (PDF)

J.A. Mielke , Tektronix, Inc. Beaverton, OR, USA
K.A. Pope , Tektronix, Inc. Beaverton, OR, USA
pp. 891-895

A fine pitch probe technology for VLSI wafer testing (PDF)

T. Tada , Mitsubishi Electr. Corp., Hyogo, Japan
R. Takagi , Mitsubishi Electr. Corp., Hyogo, Japan
S. Nakao , Mitsubishi Electr. Corp., Hyogo, Japan
M. Hyozo , Mitsubishi Electr. Corp., Hyogo, Japan
T. Arakawa , Mitsubishi Electr. Corp., Hyogo, Japan
K. Sawada , Mitsubishi Electr. Corp., Hyogo, Japan
M. Ueda , Mitsubishi Electr. Corp., Hyogo, Japan
pp. 900-906

Functional and I/sub DDQ/ testing on a static RAM (PDF)

R. Meershoek , Philips Res. Lab., Eindhoven, Netherlands
B. Verhelst , Philips Res. Lab., Eindhoven, Netherlands
R. McInerney , Philips Res. Lab., Eindhoven, Netherlands
pp. 929-937

Empirical failure analysis and validation of fault models in CMOS VLSI (PDF)

A. Pancholy , Dept. of Electr. Eng., McGill Univ., Montreal, Que., Canada
J. Rajski , Dept. of Electr. Eng., McGill Univ., Montreal, Que., Canada
pp. 938-947

On the evaluation of process-fault tolerance ability of CMOS integrated circuits (PDF)

E. Sicard , Dept. of Appl. Phys., Osaka Univ., Japan
K. Kinoshita , Dept. of Appl. Phys., Osaka Univ., Japan
pp. 948-954

A testable design of logic circuits under highly observable condition (PDF)

W. Xiaoqing , Dept. of Appl. Phys., Osaka Univ., Japan
K. Kinoshita , Dept. of Appl. Phys., Osaka Univ., Japan
pp. 955-963

Development of a new standard for test (PDF)

W.W. Sebesta , IBM Corp., Endicott, NY, USA
pp. 988-993

Wave+: An easy-to-use vector generation language for compilers (PDF)

M. Handa , VLSI Technol. Inc., San Jose, CA, USA
R.L. Steinweg , VLSI Technol. Inc., San Jose, CA, USA
pp. 994-999

Weighted random test program generation for a per-pin tester (PDF)

J. Gartner , IBM East Fishkill, Hopewell Junction, NY, USA
B. Driscoll , IBM East Fishkill, Hopewell Junction, NY, USA
D. Forlenza , IBM East Fishkill, Hopewell Junction, NY, USA
pp. 1000-1005

An empirical relationship between test transparency and fault coverage (PDF)

R.B. Elo , Intel Corp., Santa Clara, CA, USA
pp. 1006-1011

Failure coverage of functional test methods: a comparative experimental evaluation (PDF)

R. Velazco , Lab. de Genie Inf., Grenoble, France
C. Bellon , Lab. de Genie Inf., Grenoble, France
B. Martinet , Lab. de Genie Inf., Grenoble, France
pp. 1012-1017

Errors in testing (PDF)

R.H. Williams , Dept. of Electr. & Comput. Eng., New Mexico Univ., Albuquerque, NM, USA
C.F. Hawkins , Dept. of Electr. & Comput. Eng., New Mexico Univ., Albuquerque, NM, USA
pp. 1018-1027

An improved procedure to test CMOS ICs for latch-up (PDF)

R. Menozzi , DEIS, Bologna Univ., Italy
M. Lanzoni , DEIS, Bologna Univ., Italy
L. Selmi , DEIS, Bologna Univ., Italy
B. Ricco , DEIS, Bologna Univ., Italy
pp. 1028-1034

A picosecond external electro-optic prober using laser diodes (PDF)

M. Shinagawa , NTT LSI Lab., Kanagawa, Japan
T. Nagatsuma , NTT LSI Lab., Kanagawa, Japan
pp. 1035-1039

New approach to integrate LSI design databases with e-beam tester (PDF)

A. Hu , Advantest America Inc., Santa Clara, CA, USA
pp. 1040-1048

Marginal fault diagnosis based on e-beam static fault imaging with CAD interface (PDF)

N. Kuji , NTT LSI Lab., Kanagawa, Japan
K. Matsumoto , NTT LSI Lab., Kanagawa, Japan
pp. 1049-1054

Testable design and support tool for cell based test (PDF)

T. Ogihara , Mitsubishi Electr. Corp., Kanagawa, Japan
Y. Koseko , Mitsubishi Electr. Corp., Kanagawa, Japan
G. Yonemori , Mitsubishi Electr. Corp., Kanagawa, Japan
pp. 1065-1071

On automatic testpoint insertion in sequential circuits (PDF)

H.H.S. Gundlach , Inst. for Comput. Aided Circuit Design, Erlangen-Nurnberg Univ., Germany
K.-D. Muller-Glaser , Inst. for Comput. Aided Circuit Design, Erlangen-Nurnberg Univ., Germany
pp. 1072-1079

The use of tolerance intervals in the characterization of semiconductor devices (PDF)

Y.T. Hadeed , Harris Corp., Melbourne, FL, USA
K.T. Lewis , Harris Corp., Melbourne, FL, USA
pp. 924-928
79 ms
(Ver 3.3 (11022016))