The Community for Technology Leaders
1989 International Test Conference (1989)
Washington, DC, USA
Aug. 29, 1989 to Aug. 31, 1989
TABLE OF CONTENTS

Implementation and evaluation of microinstruction controlled self test using a masked microinstruction scheme (PDF)

Y. Nozuyama , Toshiba Corp., Kawasaki, Japan
A. Nishimura , Toshiba Corp., Kawasaki, Japan
J. Iwamura , Toshiba Corp., Kawasaki, Japan
pp. 625-632

Twenty years of ATE (PDF)

W. Gosling , Plessey Co. Plc, Romsey, UK
pp. 3-6

A sequential circuit fault simulation by surrogate fault propagation (PDF)

X. Wang , Dept. of Electr. & Comput. Eng., Arizona Univ., Tucson, AZ, USA
F.J. Hill , Dept. of Electr. & Comput. Eng., Arizona Univ., Tucson, AZ, USA
Z. Mi , Dept. of Electr. & Comput. Eng., Arizona Univ., Tucson, AZ, USA
pp. 9-18

The pseudoexhaustive test of sequential circuits (PDF)

H.-J. Wunderlich , Inst. of Comput. Design & Fault Tolerance, Karlsruhe Univ., West Germany
S. Hellebrand , Inst. of Comput. Design & Fault Tolerance, Karlsruhe Univ., West Germany
pp. 19-27

ESSENTIAL: an efficient self-learning test pattern generation algorithm for sequential circuits (PDF)

M.H. Schulz , Dept. of Electr. Eng., Tech. Univ. of Munich, West Germany
E. Auth , Dept. of Electr. Eng., Tech. Univ. of Munich, West Germany
pp. 28-37

An interactive sequential test pattern generation system (PDF)

R. Razdan , Digital Equipment Corp., Hudson, MA, USA
M. Anwaruddin , Digital Equipment Corp., Hudson, MA, USA
pp. 38-46

Tradeoff decisions made for a P1149.1 controller design (ATE) (PDF)

S. Vining , Texas Instrum. Inc., Plano, TX, USA
pp. 47-54

A new framework for analyzing test generation and diagnosis algorithms for wiring interconnects (PDF)

N. Jarwala , AT&T Bell Lab., Princeton, NJ, USA
C.W. Yau , AT&T Bell Lab., Princeton, NJ, USA
pp. 63-70

A unified theory for designing optimal test generation and diagnosis algorithms for board interconnects (PDF)

C.W. Yau , AT&T Bell Lab., Princeton, NJ, USA
N. Jarwala , AT&T Bell Lab., Princeton, NJ, USA
pp. 71-77

Transmission line simulation for testing ISDN devices (PDF)

D.K. Oka , LTX Corp., Westwood, MA, USA
pp. 87-93

CAE functionality for verification of diagnostic programs (PDF)

C. Pyron , Texas Instrum. Inc., Plano, TX, USA
R. Sallade , Texas Instrum. Inc., Plano, TX, USA
pp. 94-102

Topological testing (PDF)

M. Malek , Dept. of Electr. & Comput. Eng., Texas Univ., Austin, TX, USA
A. Mourad , Dept. of Electr. & Comput. Eng., Texas Univ., Austin, TX, USA
M. Pandya , Dept. of Electr. & Comput. Eng., Texas Univ., Austin, TX, USA
pp. 103-110

Fast accurate and complete ADC testing (PDF)

S. Max , LTX Corp., Westwood, MA, USA
pp. 111-117

Fault diagnosis in analogue circuits using AI techniques (PDF)

A. McKeon , Dept. of Electr. Eng., Imperial Coll. of Sci., Technol., & Med., London, UK
pp. 118-123

High-resolution analog measurement on mixed signal LSI tester (PDF)

K. Akiyama , Yokogawa Hewlett-Packard, Tokyo, Japan
H. Nishimura , Yokogawa Hewlett-Packard, Tokyo, Japan
K. Anazawa , Yokogawa Hewlett-Packard, Tokyo, Japan
A. Kishida , Yokogawa Hewlett-Packard, Tokyo, Japan
N. Kasuga , Yokogawa Hewlett-Packard, Tokyo, Japan
pp. 124-128

Delay test generation for synchronous sequential circuits (PDF)

S. Devadas , Dept. of Electr. Eng. & Comput. Sci., MIT, Cambridge, MA, USA
pp. 144-152

Computation of delay defect and delay fault probabilities using a statistical timing simulator (PDF)

J. Benkoski , Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
A.J. Strojwas , Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
pp. 153-160

Enhanced delay test generator for high-speed logic LSIs (PDF)

K. Hatayama , Hitachi Ltd., Ibaraki, Japan
M. Ikeda , Hitachi Ltd., Ibaraki, Japan
T. Hayashi , Hitachi Ltd., Ibaraki, Japan
pp. 161-165

Prototype testing simplified by scannable buffers and latches (PDF)

A. Halliday , Texas Instrum. Inc., Plano, TX, USA
G. Young , Texas Instrum. Inc., Plano, TX, USA
A. Crouch , Texas Instrum. Inc., Plano, TX, USA
pp. 174-181

Board-level boundary-scan: regaining observability with an additional IC (PDF)

W.D. Ballew , AT&T-NS, Oklahoma City, OK, USA
L.M. Streb , AT&T-NS, Oklahoma City, OK, USA
pp. 182-189

Coupling coefficients for signal lines separated by ground lines on PC boards (PDF)

J.R. Birchak , Reliability Inc., Houston, TX, USA
H.K. Haill , Reliability Inc., Houston, TX, USA
pp. 190-198

Clock signal distribution network for high speed testers (PDF)

C.-W. Hsue , AT&T Bell Lab., Princeton, NJ, USA
pp. 199-207

An analysis of tungsten probes' effect on yield in a production wafer probe environment (PDF)

N. Nadeau , Mitel SCC, Bromont, Que., Canada
S. Perreault , Mitel SCC, Bromont, Que., Canada
pp. 208-215

A telecommunications line interface test system architecture (PDF)

J.L. LaMay , Crystal Semicond. Corp., Austin, TX, USA
D.C. Caldwell , Crystal Semicond. Corp., Austin, TX, USA
pp. 216-221

Engineering curricular for 'meeting the tests of time' (PDF)

R. Absher , Dept. of Comput. Sci. & Electr. Eng., Vermont Univ., Burlington, VT, USA
J.E. Lecky , Dept. of Comput. Sci. & Electr. Eng., Vermont Univ., Burlington, VT, USA
pp. 242-244

Design and test in the universities (PDF)

S.A. Al-Arian , Dept. of Comput. Sci. & Eng., South Florida Univ., Tampa, FL, USA
pp. 245

The push for test in universities (PDF)

D.W. Bouldin , Electr. & Comput. Eng., Tennessee Univ., Knoxsville, TN, USA
pp. 246

Design assurance in a university setting (PDF)

K. Rose , Rensselaer Polytech. Inst., Troy, NY, USA
pp. 247-248

A fundamental approach to SPC implementation (PDF)

M.N. Vittrup , Westinghouse Electr. Corp., College Station, TX, USA
G.S. Frashure , Westinghouse Electr. Corp., College Station, TX, USA
pp. 249-251

Test set embedding in a built-in self-test environment (PDF)

S.B. Akers , Dept. of Electr. & Comput. Eng., Massachusetts Univ., Amherst, MA, USA
pp. 257-263

Hardware-based weighted random pattern generation for boundary scan (PDF)

F. Brglez , Microelectron. Center of North Carolina, Research Triangle Park, NC, USA
C. Gloster , Microelectron. Center of North Carolina, Research Triangle Park, NC, USA
G. Kedem , Microelectron. Center of North Carolina, Research Triangle Park, NC, USA
pp. 264-274

A self-test system architecture for reconfigurable WSI (PDF)

D.L. Landis , Dept. of Electr. Eng., South Florida Univ., Tampa, FL, USA
pp. 275-282

Techniques for improved testability in the IBM ES/9370 system (PDF)

R.F. Lusch , IBM Corp., Endicott, NY, USA
E.F. Sarkany , IBM Corp., Endicott, NY, USA
pp. 290-294

The role of test in a 'continuous improvement' environment (PDF)

R. Santella , GenRad Inc., Concord, MA, USA
pp. 304-308

Design for test of Mbit DRAMs (PDF)

R. Kraus , Uni Bw Munich, West Germany
O. Kowarik , Uni Bw Munich, West Germany
K. Hoffmann , Uni Bw Munich, West Germany
pp. 316-321

A new array architecture for parallel testing in VLSI memories (PDF)

Y. Matsuda , Mitsubishi Electr. Corp., Hyogo, Japan
K. Arimoto , Mitsubishi Electr. Corp., Hyogo, Japan
M. Tsukude , Mitsubishi Electr. Corp., Hyogo, Japan
T. Oishi , Mitsubishi Electr. Corp., Hyogo, Japan
K. Fujishima , Mitsubishi Electr. Corp., Hyogo, Japan
pp. 322-326

Design of a BIST RAM with row/column pattern sensitive fault detection capability (PDF)

M. Franklin , Wisconsin Univ., Madison, WI, USA
K.K. Saluja , Wisconsin Univ., Madison, WI, USA
pp. 327-336

The analysis of parallel BIST by the combined Markov chain (CMC) model (PDF)

C.C. Chuang , Digital Equip. Corp., Marlboro, MA, USA
A.K. Gupta , Digital Equip. Corp., Marlboro, MA, USA
pp. 337-343

Experiments on aliasing in signature analysis registers (PDF)

D. Xavier , Dept. of Electr. Eng., McGill Univ., Montreal, Que., Canada
R.C. Aitken , Dept. of Electr. Eng., McGill Univ., Montreal, Que., Canada
pp. 344-354

Optimized synthesis of dedicated controllers with concurrent checking capabilities (PDF)

R. Leveugle , Inst. Nat. Polytech. de Grenoble/CSI, France
G. Saucier , Inst. Nat. Polytech. de Grenoble/CSI, France
pp. 355-363

Testability analysis of synchronous sequential circuits based on structural data (PDF)

R.V. Hudli , Dept. of Comput. Sci., Nebraska Univ., Lincoln, NE, USA
S.C. Seth , Dept. of Comput. Sci., Nebraska Univ., Lincoln, NE, USA
pp. 364-372

An approach to functional level testability analysis (PDF)

C.H. Chen , Dept. of Electr. & Comput. Eng., Massachusetts Univ., Amherst, MA, USA
P.R. Menon , Dept. of Electr. & Comput. Eng., Massachusetts Univ., Amherst, MA, USA
pp. 373-380

An easily computed functional level testability measure (PDF)

K. Thearling , Coordinated Sci. Lab., Illinois Univ., Urbana, IL, USA
pp. 381-390

A testing technique to characterize E/sup 2/PROM's aging and endurance (PDF)

M. Lanzoni , DEIS, Bologna Univ., Italy
P. Olivo , DEIS, Bologna Univ., Italy
B. Ricco , DEIS, Bologna Univ., Italy
pp. 391-396

Quality issues of high pin count fine pitch VLSI packages (PDF)

E.R. Hnatek , Viking Labs./Honeywell, Mountain View, CA, USA
pp. 397-421

CMOS IC stuck-open-fault electrical effects and design considerations (PDF)

J.M. Soden , Sandia Nat. Lab., Albuquerque, NM, USA
R.K. Treece , Sandia Nat. Lab., Albuquerque, NM, USA
M.R. Taylor , Sandia Nat. Lab., Albuquerque, NM, USA
pp. 423-430

Fast automatic failbit analysis for DRAMs (PDF)

W. Malzfeldt , Siemens AG, Munich, West Germany
W. Mohr , Siemens AG, Munich, West Germany
H.-D. Oberle , Siemens AG, Munich, West Germany
pp. 431-438

Testing for coupled cells in random-access memories (PDF)

J. Savir , IBM, Poughkeepsie, NY, USA
W.H. McAnney , IBM, Poughkeepsie, NY, USA
pp. 439-451

A testing methodology for new-generation specialty memory devices (PDF)

K. Koo , Teradyne Inc., Agoura Hills, CA, USA
S. Ramseyer , Teradyne Inc., Agoura Hills, CA, USA
A. Tejeda , Teradyne Inc., Agoura Hills, CA, USA
pp. 452-460

Hierarchical test pattern generation based on high-level primitives (PDF)

T.M. Sarfert , Siemens AG, Munich, West Germany
R. Markgraf , Siemens AG, Munich, West Germany
E. Trischler , Siemens AG, Munich, West Germany
pp. 470-479

A framework and method for hierarchical test generation (PDF)

J.D. Calhoun , Microelectron. Center of North Carolina, Research Triangle Park, NC, USA
F. Brglez , Microelectron. Center of North Carolina, Research Triangle Park, NC, USA
pp. 480-490

Redundancies and don't cares in sequential logic synthesis (PDF)

S. Devadas , Dept. of Electr. Eng. & Comput. Sci., MIT, Cambridge, MA, USA
pp. 491-500

Synthesis of pseudo-random pattern testable designs (PDF)

V.S. Iyengar , IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA
D. Brand , IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA
pp. 501-508

A testable realization of CMOS combinational circuits (PDF)

S. Chakravarty , Dept. of Comput. Sci., State Univ. of New York, Buffalo, NY, USA
pp. 509-518

Process monitoring oriented IC testing (PDF)

W. Maly , Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
S.B. Naik , Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
pp. 527-532

Improved system design through proper nesting of test levels (PDF)

J. Patterson , AT&T Bell Labs., North Andover, MA, USA
pp. 533-542

The linear array systolic tester (LAST) (PDF)

G. Lesmeister , ASIX Syst. Corp., Fremont, CA, USA
pp. 543-549

An integrated analog test simulation environment (PDF)

B.A. Webster , Teradyne Inc., Boston, MA, USA
pp. 567-571

The Omnitest system: a no-generate, no-compile, interactive test methodology (PDF)

W.D. Dettloff , Microelectron. Center of North Carolina, Research Triangle Park, NC, USA
M.D. Tebbs , Microelectron. Center of North Carolina, Research Triangle Park, NC, USA
pp. 572-576

SASPL: a test program productivity analysis tool (PDF)

E. Paradis , Mitel SCC, Bromont, Que., Canada
D. Stannard , Mitel SCC, Bromont, Que., Canada
pp. 577-584

Cost impacts of automatic test equipment purchase decisions (PDF)

J.S. Pabst , LTX/Trillium, San Jose, CA, USA
pp. 605-610

Testability features of the MC68332 modular microcontroller (PDF)

W. Harwood , Motorola Inc., Austin, TX, USA
M. McDermott , Motorola Inc., Austin, TX, USA
pp. 615-623

Fantestic: towards a powerful fault analysis and test pattern generator for integrated circuits (PDF)

M. Jacomet , Dept. of Electr. Eng., Swiss Federal Inst. of Technol., Zurich, Switzerland
pp. 633-642

Test effectiveness metrics for CMOS faults (PDF)

S.F. Midkiff , Dept. of Electr. Eng., Virginia Polytech. Inst. & State Univ., Blacksburg, VA, USA
W.-Y. Koe , Dept. of Electr. Eng., Virginia Polytech. Inst. & State Univ., Blacksburg, VA, USA
pp. 653-659

A testability strategy for silicon compilers (PDF)

F. Beenker , Philips Res. Lab., Eindhoven, Netherlands
R. Dekker , Philips Res. Lab., Eindhoven, Netherlands
R. Stans , Philips Res. Lab., Eindhoven, Netherlands
pp. 660-669

Location and identification for single and multiple faults in testable redundant PLAs for yield enhancement (PDF)

Y.-N. Shen , Dept. of Comput. Sci., Texas A&M Univ., College Station, TX, USA
F. Lombardi , Dept. of Comput. Sci., Texas A&M Univ., College Station, TX, USA
pp. 670-678

Fault location in repairable programmable logic arrays (PDF)

C.-L. Way , Dept. of Electr. Eng., Michigan State Univ., East Lansing, MI, USA
pp. 679-685

Testability expertise and test planning from high-level specifications (PDF)

M. Crastes de Paulet , Inst. Nat. Polytech. de Grenoble, France
M. Karam , Inst. Nat. Polytech. de Grenoble, France
G. Saucier , Inst. Nat. Polytech. de Grenoble, France
pp. 692-699

Testing of glue logic interconnects using boundary scan architecture (PDF)

A. Hassan , Dept. of Electr. Eng., McGill Univ., Montreal, Que., Canada
V.K. Agarwal , Dept. of Electr. Eng., McGill Univ., Montreal, Que., Canada
J. Rajski , Dept. of Electr. Eng., McGill Univ., Montreal, Que., Canada
pp. 700-711

The parallel-test-detect fault simulation algorithm (PDF)

B. Underwood , Microelectron. & Comput. Technol. Corp., Austin, TX, USA
J. Ferguson , Microelectron. & Comput. Technol. Corp., Austin, TX, USA
pp. 712-717

Fault partitioning issues in an integrated parallel test generation/fault simulation environment (PDF)

S. Patil , Coordinated Sci. Lab., Illinois Univ., Urbana, IL, USA
P. Banerjee , Coordinated Sci. Lab., Illinois Univ., Urbana, IL, USA
pp. 718-726

Fault simulation in a pipelined multiprocessor system (PDF)

P. Agrawal , AT&T Bell Lab., Murray Hill, NJ, USA
V.D. Agrawal , AT&T Bell Lab., Murray Hill, NJ, USA
K.-T. Cheng , AT&T Bell Lab., Murray Hill, NJ, USA
R. Tutundjian , AT&T Bell Lab., Murray Hill, NJ, USA
pp. 727-734

Built in self test of the Macrolan chip (PDF)

R. Illman , ICL Mainframe Syst. Div., Manchester, UK
S. Clarke , ICL Mainframe Syst. Div., Manchester, UK
pp. 735-744

A pragmatic approach to the design of self-testing circuits (PDF)

Y. Savaria , Dept. of Electr. Eng., Ecole Polytech. de Montreal, Que., Canada
B. Lague , Dept. of Electr. Eng., Ecole Polytech. de Montreal, Que., Canada
B. Kaminska , Dept. of Electr. Eng., Ecole Polytech. de Montreal, Que., Canada
pp. 745-754

A BIST design methodology experiment (PDF)

S.H. Duncan , Digital Equipment Corp., Littleton, MA, USA
pp. 755-762

A new system architecture for a combined in-circuit/functional tester (PDF)

J.M. Stepleton , Hewlett Packard, Amstelveen, Netherlands
pp. 763-772

Flexible, high-performance pin electronics implementation (PDF)

P.N. King , Hewlett Packard, Loveland, CO, USA
pp. 787-794

Efficient generation of test patterns using Boolean difference (PDF)

T. Larrabee , Dept. of Comput. Sci., Stanford Univ., CA, USA
pp. 795-801

Search strategy switching: an alternative to increased backtracking (PDF)

H.B. Min , Dept. of Electr. & Comput. Eng., Texas Univ., Austin, TX, USA
W.A. Rogers , Dept. of Electr. & Comput. Eng., Texas Univ., Austin, TX, USA
pp. 803-811

Automating ASIC design-for-testability-the VLSI Test Assistant (PDF)

A. Samad , VLSI Technol. Inc., San Jose, CA, USA
M. Bell , VLSI Technol. Inc., San Jose, CA, USA
pp. 819-828

'ATG' test generation software (PDF)

A.E. Downey , Ando Corp., Sunnyvale, CA, USA
pp. 829-837

On the design and test of asynchronous macros embedded in synchronous systems (PDF)

J. Leenstra , Inst. for Microelectron., Stuttgart, West Germany
L. Spaanenburg , Inst. for Microelectron., Stuttgart, West Germany
pp. 838-845

A high performance, 10-volt integrated pin electronics driver (PDF)

C. Branson , Tektronix Inc., Beaverton, OR, USA
pp. 846-853

Custom pin electronics for VLSI automatic test equipment (PDF)

S.W. Bryson , Trillium, San Jose, CA, USA
pp. 854-859

The economics of scan design (PDF)

M.E. Levitt , Illinois Univ., Urbana, IL, USA
pp. 869-874

Cost analysis of test method environments (PDF)

C. Dislis , Brunel Univ., Uxbridge, UK
I.D. Dear , Brunel Univ., Uxbridge, UK
J.R. Miles , Brunel Univ., Uxbridge, UK
S.C. Lau , Brunel Univ., Uxbridge, UK
A.P. Ambler , Brunel Univ., Uxbridge, UK
pp. 875-883

Design-for-testability using test design yield and decision theory (PDF)

B. Kaminska , Dept. of Electr. Eng., Ecole Polytech. de Montreal, Que., Canada
Y. Savaria , Dept. of Electr. Eng., Ecole Polytech. de Montreal, Que., Canada
pp. 884-892

Design Test: a solution to the problems of ASIC verification (PDF)

D. Allingham , NCR Microelectron., Fort Collins, CO, USA
P. Bashford , NCR Microelectron., Fort Collins, CO, USA
M. Peters , NCR Microelectron., Fort Collins, CO, USA
D. Vendl , NCR Microelectron., Fort Collins, CO, USA
pp. 893-902

CrossCheck-a practical solution for ASIC testability (PDF)

G. Swan , CrossCheck Technol. Inc., San Jose, CA, USA
Y. Trivedi , CrossCheck Technol. Inc., San Jose, CA, USA
D. Wharton , CrossCheck Technol. Inc., San Jose, CA, USA
pp. 903-908

Cell-based test design method (PDF)

K. Sakashita , Mitsubishi Electr. Corp., Hyogo, Japan
T. Hashizume , Mitsubishi Electr. Corp., Hyogo, Japan
T. Ohya , Mitsubishi Electr. Corp., Hyogo, Japan
I. Takimoto , Mitsubishi Electr. Corp., Hyogo, Japan
S. Kato , Mitsubishi Electr. Corp., Hyogo, Japan
pp. 909-916

A logic analyzer tool that cuts e-beam prober acquisition times (PDF)

C.G. Talbot , Schlumberger Technol. ATE, San Jose, CA, USA
S. Rajan , Schlumberger Technol. ATE, San Jose, CA, USA
pp. 923-927

Rapid data acquisition for e-beam testing (PDF)

D.J. Hall , Cambridge Instrum. Ltd., UK
A.W. Sloman , Cambridge Instrum. Ltd., UK
G.S. Plows , Cambridge Instrum. Ltd., UK
pp. 928-933

CMOS design for improved IC testability (PDF)

M. Favalli , DEIS, Bologna Univ., Italy
P. Olivo , DEIS, Bologna Univ., Italy
M. Damiani , DEIS, Bologna Univ., Italy
B. Ricco , DEIS, Bologna Univ., Italy
pp. 934

Diagnostics based on faulty signature (PDF)

J.C. Chan , IBM Corp., Austin, TX, USA
pp. 935

TSG-a test system generator for debugging and regression test of high-level behavioral synthesis tools (PDF)

R. Ernst , AT&T Bell Labs., Allentown, PA, USA
S. Sutarwala , AT&T Bell Labs., Allentown, PA, USA
pp. 937

VLSI package reliability risk due to accelerated environmental testing (PDF)

D. Haupert , Control Data Corp., St. Paul, MN, USA
F.-G. Chen , Control Data Corp., St. Paul, MN, USA
D. Lee , Control Data Corp., St. Paul, MN, USA
pp. 938

How much fault coverage is enough? (PDF)

B. Henshaw , NCR Corp., Wichita, KS, USA
pp. 939

Fault diagnosis based on post-test fault dictionary generation (PDF)

J. Kato , NEC Corp., Tokyo, Japan
T. Shimono , NEC Corp., Tokyo, Japan
M. Kawai , NEC Corp., Tokyo, Japan
pp. 940

Parallel automated test pattern generation on the Connection Machine (PDF)

P. Mayor , Dept. of Electr. & Comput. Eng., Syracuse Univ., NY, USA
V. Pitchumani , Dept. of Electr. & Comput. Eng., Syracuse Univ., NY, USA
V. Narayanan , Dept. of Electr. & Comput. Eng., Syracuse Univ., NY, USA
pp. 942

Standard testability bus-an applications example (PDF)

J. Turino , Logical Solutions Technol. Inc., Campbell, CA, USA
pp. 943

Testing and testability of programmable logic devices (PDF)

J.M. VanDerwiele , AT&T Network Syst., Oklahoma City, OK, USA
pp. 944

FUNTEST: a functional automatic test pattern generator for combinational circuits (PDF)

S.A. Al-Arian , Dept. of Comput. Sci. & Eng., South Florida Univ., Tampa, FL, USA
pp. 945-946

Detection of transient faults in microprocessors by concurrent monitoring (PDF)

M.Z. Khan , Dept. of Electr. Eng., Virginia Polytch. Inst. & State Univ., Blacksburg, VA, USA
J.G. Tront , Dept. of Electr. Eng., Virginia Polytch. Inst. & State Univ., Blacksburg, VA, USA
pp. 948

Model engineering curricula for 'meeting the tests of time' (PDF)

R. Absher , Dept. of Comput. Sci. & Electr. Eng., Vermont Univ., Burlington, VT, USA
J.E. Lecky , Dept. of Comput. Sci. & Electr. Eng., Vermont Univ., Burlington, VT, USA
pp. 949

Combinational and sequential circuit fault diagnosis using AI techniques (PDF)

B. Rogel-Favila , Dept. of Electr. Eng., Imperial Coll. of Sci., Technol. & Med., London, UK
P.Y.K. Cheung , Dept. of Electr. Eng., Imperial Coll. of Sci., Technol. & Med., London, UK
pp. 950

A military test method for measuring fault coverage (PDF)

W.H. Debany , US Air Force Rome Air Dev. Center, Griffiss AFB, NY, USA
pp. 951

Achieving ATE accuracy at gigahertz test rates: comparison of electronic and electrooptic sampling technologies (PDF)

F.J. Henley , Photon Dynamics Inc., San Jose, CA, USA
H.-J. Choi , Photon Dynamics Inc., San Jose, CA, USA
pp. 953

Signature analysis with non-linear feedback shift registers (PDF)

P.N. Marinos , Dept. of Electr. Eng., Duke Univ., Durham, NC, USA
R. Raina , Dept. of Electr. Eng., Duke Univ., Durham, NC, USA
pp. 954-955

Test and design for testability of reconvergent fan-out CMOS logic networks (PDF)

F. Darlay , IMAG/TIM3 Lab., Grenoble, France
B. Courtois , IMAG/TIM3 Lab., Grenoble, France
pp. 956
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