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2015 ACM/IEEE International Workshop on System Level Interconnect Prediction (SLIP) (2015)
San Francisco, CA, USA
June 6, 2015 to June 6, 2015
ISBN: 978-1-4673-8189-5
TABLE OF CONTENTS

Copyright (PDF)

pp. 1

SI for free: machine learning of interconnect coupling delay and transition effects (Abstract)

Andrew B. Kahng , ECE UC San Diego, La Jolla, CA, USA
Mulong Luo , CSE Departments, UC San Diego, La Jolla, CA, USA
Siddhartha Nath , CSE Departments, UC San Diego, La Jolla, CA, USA
pp. 1-8

Smart I/Os: a data-pattern aware 2.5D interconnect with space-time multiplexing (Abstract)

Sai Manoj , School of Electrical and Electronic Engineering Nanyang Technological University, Singapore
Kanwen Wang , School of Electrical and Electronic Engineering Nanyang Technological University, Singapore
Hantao Huang , School of Electrical and Electronic Engineering Nanyang Technological University, Singapore
Hao Yu , School of Electrical and Electronic Engineering Nanyang Technological University, Singapore
pp. 1-6

Compact modeling and system implications of microring modulators in nanophotonic interconnects (Abstract)

Rui Wu , Department of Electrical & Computer Engineering, University of California, Santa Barbara, CA, US
Chin-Hui Chen , HP Labs, Hewlett-Packard Company, Palo Alto, CA, US
Jean-Marc Fedeli , CEA, LETI, Minatec Campus, Grenoble, France
Maryse Fournier , CEA, LETI, Minatec Campus, Grenoble, France
Raymond G. Beausoleil , HP Labs, Hewlett-Packard Company, Palo Alto, CA, US
Kwang-Ting Cheng , Department of Electrical & Computer Engineering, University of California, Santa Barbara, CA, US
pp. 1-6

Clock clustering and IO optimization for 3D integration (Abstract)

Samyoung Bang , Samsung Electronics Co. Ltd, Hwaseong-si, South Korea
Kwangsoo Han , ECE UC San Diego, La Jolla, CA, USA
Andrew B. Kahng , CSE Departments, UC San Diego, La Jolla, CA, USA
Vaishnav Srinivas , ECE UC San Diego, La Jolla, CA, USA
pp. 1-8

On fast timing closure: speeding up incremental path-based timing analysis with mapreduce (Abstract)

, Department of Electrical and Computer Engineering, University of Illinois at Urbana-Champaign, IL, USA
, Department of Electrical and Computer Engineering, University of Illinois at Urbana-Champaign, IL, USA
pp. 1-6

Power line communication for hybrid power/signal pin SOC design (Abstract)

Xiang Zhang , ECE Dept., University of California, San Diego, CA, USA
Yang Liu , Institute of Electronic CAD, Xidian University, Xi?an, China
Ryan Coutts , ECE Dept., University of California, San Diego, CA, USA
, CSE and ECE Dept., University of California, San Diego, CA, USA
pp. 1-8

Lynx: a self-organizing wireless sensor network with commodity palmtop computers (Abstract)

Haifeng Xu , University of Pittsburgh, Pittsburgh, PA, USA
Melissa M. Bilec , University of Pittsburgh, Pittsburgh, PA, USA
William O. Collinge , University of Pittsburgh, Pittsburgh, PA, USA
Laura A. Schaefer , University of Pittsburgh, Pittsburgh, PA, USA
Amy E. Landis , Arizona State University, Tempe, AZ, USA
Alex K. Jones , University of Pittsburgh, Pittsburgh, PA, USA
pp. 1-7

Multi-product floorplan and uncore design framework for chip multiprocessors (Abstract)

Marco Escalante , Intel Corp., Hillsboro, OR
Andrew B. Kahng , ECE and CSE Departments, University of California at San Diego
Michael Kishinevsky , Intel Corp., Hillsboro, OR
Umit Ogras , School of ECEE, Arizona State University
Kambiz Samadi , Qualcomm Research, San Diego, CA
pp. 1-7
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