The Community for Technology Leaders
2014 ACM/IEEE International Workshop on System Level Interconnect Prediction (SLIP) (2014)
TX, USA
June 1, 2014 to June 1, 2014
TABLE OF CONTENTS

Power network-on-chip for scalable power delivery (Abstract)

Inna Vaisband , Department of Electrical and Computer Engineering, University of Rochester, New York 14627, USA
Eby G. Friedman , Department of Electrical and Computer Engineering, University of Rochester, New York 14627, USA
pp. 1-5

Range-based dynamic routing of hierarchical on chip network traffic (Abstract)

Julian Kemmerer , Electrical and Computer Engineering Department, Drexel University, Philadelphia, Pennsylvania 19104, USA
Baris Taskin , Electrical and Computer Engineering Department, Drexel University, Philadelphia, Pennsylvania 19104, USA
pp. 1-8

Methodology for electromigration signoff in the presence of adaptive voltage scaling (Abstract)

Wei-Ting Jonas Chan , ECE Departments, UC San Diego, La Jolla, CA 92093, USA
Andrew B. Kahng , ECE Departments, UC San Diego, La Jolla, CA 92093, USA
Siddhartha Nath , CSE Departments, UC San Diego, La Jolla, CA 92093, USA
pp. 1-7

Compact models and model standard for 2.5D and 3D integration (Abstract)

Qiaosha Zou , Computer Science and Engineering, The Pennsylvania State University, USA
Yuan Xie , Computer Science and Engineering, The Pennsylvania State University, USA
pp. 1-7

Worst-case noise area prediciton of on-chip power distribution network (Abstract)

Xiang Zhang , ECE Dept., University of California, San Diego, CA, USA
Jingwei Lu , CSE Dept, University of California, San Diego, CA, USA
Yang Liu , Institute of Electronic CAD, Xidian University, Xi'an, China
Chung-Kuan Cheng , CSE Dept, University of California, San Diego, CA, USA
pp. 1-8

Pacman: driving nonuniform clock grid loads for low-skew robust clock network (Abstract)

Nancy Y. Zhou , IBM Systems & Technology Group, 11400 Burnet Road, Austin, TX 78758
Phillip Restle , IBM Waston Research Laboratory, 11501 Burnet Road, Austin, TX 78758
Joseph Palumbo , IBM Waston Research Laboratory, 11501 Burnet Road, Austin, TX 78758
Joseph Kozhaya , IBM Systems & Technology Group, 11400 Burnet Road, Austin, TX 78758
Haifeng Qian , IBM Waston Research Laboratory, 11501 Burnet Road, Austin, TX 78758
Zhou Li , IBM Waston Research Laboratory, 11501 Burnet Road, Austin, TX 78758
Charles J. Alpert , IBM Waston Research Laboratory, 11501 Burnet Road, Austin, TX 78758
Cliff Sze , IBM Waston Research Laboratory, 11501 Burnet Road, Austin, TX 78758
pp. 1-5

UI-route: An ultra-fast incremental maze routing algorithm (Abstract)

Tsung-Wei Huang , Department of Electrical and Computer Engineering, University of Illinois at Urbana-Champaign, IL, USA
Pei-Ci Wu , Department of Electrical and Computer Engineering, University of Illinois at Urbana-Champaign, IL, USA
Martin D. Wong , Department of Electrical and Computer Engineering, University of Illinois at Urbana-Champaign, IL, USA
pp. 1-8

Methodology for electromigration signoff in the presence of adaptive voltage scaling (Abstract)

Wei-Ting Chan , ECE, UC San Diego, La Jolla, CA, USA
Andrew B. Kahng , CSE, UC San Diego, La Jolla, CA, USA
Siddhartha Nath , CSE, UC San Diego, La Jolla, CA, USA
pp. 1-7
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