Cover Art (PDF)

Title Page i (PDF)

Title Page iii (PDF)

Copyright Page (PDF)

Table of Contents (PDF)

Message from the Chairs (PDF)

Conference Committees (PDF)

Additional Reviewers (PDF)

MinBD: Minimally-Buffered Deflection Routing for Energy-Efficient Interconnect (Abstract)

Déjà Vu Switching for Multiplane NoCs (Abstract)

HARAQ: Congestion-Aware Learning Model for Highly Adaptive Routing Algorithm in On-Chip Networks (Abstract)

Overlaid Mesh Topology Design and Deadlock Free Routing in Wireless Network-on-Chip (Abstract)

An Optimal Control Approach to Power Management for Multi-Voltage and Frequency Islands Multiprocessor Platforms under Highly Variable Workloads (Abstract)

In-network Monitoring and Control Policy for DVFS of CMP Networks-on-Chip and Last Level Caches (Abstract)

Modeling and Power Evaluation of On-Chip Router Components in Spintronics (Abstract)

Heterogeneous NoC Design for Efficient Broadcast-based Coherence Protocol Support (Abstract)

CCNoC: Specializing On-Chip Interconnects for Energy Efficiency in Cache-Coherent Servers (Abstract)

Synthesis of NoC Interconnects for Custom MPSoC Architectures (Abstract)

Hierarchical Network-on-Chip and Traffic Compression for Spiking Neural Network Implementations (Abstract)

Reservation-based Network-on-Chip Timing Models for Large-scale Architectural Simulation (Abstract)

TOPAZ: An Open-Source Interconnection Network Simulator for Chip Multiprocessors and Supercomputers (Abstract)

Analytical Performance Modeling of Hierarchical Interconnect Fabrics (Abstract)

Dynamic Flow Regulation for IP Integration on Network-on-Chip (Abstract)

A Novel Flit Serialization Strategy to Utilize Partially Faulty Links in Networks-on-Chip (Abstract)

Fine-Grained Bandwidth Adaptivity in Networks-on-Chip Using Bidirectional Channels (Abstract)

Efficient Timing Channel Protection for On-Chip Networks (Abstract)

A Statically Scheduled Time-Division-Multiplexed Network-on-Chip for Real-Time Systems (Abstract)

A Mixed Verification Strategy Tailored for Networks on Chip (Abstract)

Transient and Permanent Error Control for High-End Multiprocessor Systems-on-Chip (Abstract)

Generic Monitoring and Management Infrastructure for 3D NoC-Bus Hybrid Architectures (Abstract)

Engineering a Bandwidth-Scalable Optical Layer for a 3D Multi-core Processor with Awareness of Layout Constraints (Abstract)

A Hybrid Buffer Design with STT-MRAM for On-Chip Interconnects (Abstract)

DSENT - A Tool Connecting Emerging Photonics with Electronics for Opto-Electronic Networks-on-Chip Modeling (Abstract)

Author Index (PDF)

Publisher's Information (PDF)