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Proceedings of IEEE 9th International Workshop on Hardware Software C-Design/CASHE (2001)
Copenhagen, Denmark
April 25, 2001 to April 27, 2001
ISBN: 1-58113-364-2
TABLE OF CONTENTS

Embedded UML: a merger of real-time UML and co-design (Abstract)

G. Martin , Cadence Design Syst. Inc., San Jose, CA, USA
pp. 23-28

A practical tool box for system level communication synthesis (Abstract)

D. Hommais , Equipe ASIM, Univ. Pierre et Marie Curie, Paris, France
pp. 48-53

RS-FDRA: a register sensitive software pipelining algorithm for embedded VLIW processors (Abstract)

C. Akturan , Dept. of Electr. & Comput. Eng., Texas Univ., Austin, TX, USA
pp. 67-72

A novel parallel deadlock detection algorithm and architecture (Abstract)

P.H. Shiu , Electr. & Comput. Eng., Georgia Inst. of Technol., Atlanta, GA, USA
pp. 73-78

Towards effective embedded processors in codesigns: customizable partitioned caches (Abstract)

P. Petrov , Dept. of Comput. Sci. & Eng., California Univ., San Diego, La Jolla, CA, USA
pp. 79-84

Minimizing system modification in an incremental design approach (Abstract)

P. Pop , Dept. of Comput. & Inf. Sci., Linkoping Univ., Sweden
pp. 183-188

The TACO protocol processor simulation environment (Abstract)

S. Virtanen , Turku Centre for Comput. Sci., Finland
pp. 201-206

Compiler-directed selection of dynamic memory layouts (Abstract)

M. Kandemir , Pennsylvania State Univ., University Park, PA, USA
pp. 219-224

Dynamic I/O power management for hard real-time systems (Abstract)

V. Swaminathan , Dept. of Electr. & Comput. Eng., Duke Univ., Durham, NC, USA
pp. 237-242

Hybrid global/local search strategies for dynamic voltage scaling in embedded multiprocessors (Abstract)

N.K. Bambha , Dept. of Electr. & Comput. Eng., Maryland Univ., Baltimore, MD, USA
pp. 243-248

Processor frequency setting for energy minimization of streaming multimedia application (Abstract)

A. Acquaviva , Dipartimento di Elettronica Inf. e Sistemistica, Bologna Univ., Italy
pp. 249-253

A design framework to efficiently explore energy-delay tradeoffs (Abstract)

W. Fornaciari , Dipartimento di Elettronica, Politecnico di Milano, Italy
pp. 260-265
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