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Proceedings of the Eighth International Workshop on Hardware/Software Codesign. CODES 2000 (2000)
San Diego, CA, USA
May 5, 2000 to May 5, 2000
ISBN: 1-58113-268-9
TABLE OF CONTENTS

Towards a new standard for system-level design (Abstract)

S.Y. Liao , Adv. Technol. Group, Synopsys Inc., USA
pp. 2-6

Modeling industrial embedded systems with UML (Abstract)

J.M. Fernandes , Dept. of Inf., Minho Univ., Braga, Portugal
pp. 18-22

Instruction-level power estimation for embedded VLIW cores (PDF)

M. Sami , Dipt. di Elettronica e Inf., Politecnico di Milano, Italy
pp. 34-38

Low-power task scheduling for multiple devices (Abstract)

Yung-Hsiang Lu , Comput. Syst. Lab., Stanford Univ., CA, USA
pp. 39-43

Co-design of interleaved memory systems (Abstract)

Hua Lin , Dept. of Electr. Eng., Princeton Univ., NJ, USA
pp. 46-50

Performance estimation for embedded systems with data and control dependencies (PDF)

P. Pop , Dept. of Comput. & Inf. Sci., Linkoping Univ., Sweden
pp. 62-66

Program path analysis to bound cache-related preemption delay in preemptive real-time systems (PDF)

H. Tomiyama , Center for Embedded Comput. Syst., California Univ., Irvine, CA, USA
pp. 67-71

Fast performance prediction for periodic task systems (Abstract)

Xiaobo Hu , Dept. of Comput. Sci. & Eng., Notre Dame Univ., IN, USA
pp. 72-76

A method to derive application-specific embedded processing cores (PDF)

O. Hebert , Dept. of Electr. & Comput. Eng., Ecole Polytech., Montreal, Que., Canada
pp. 88-92

Linking codesign and reuse in embedded systems design (PDF)

M. Meerwein , Autom. Equip. Div., Robert Bosch GmbH, Stuttgart, Germany
pp. 93-97

Parameterized system design (PDF)

T.D. Givargis , Dept. of Comput. Sci. & Eng., California Univ., Riverside, CA, USA
pp. 98-102

Task response time optimization using cost-based operation motion (Abstract)

B. Tabbara , Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
pp. 110-114

Heuristic tradeoffs between latency and energy consumption in register assignment (Abstract)

R. Anand , Dept. of Electr. & Comput. Eng., Texas Univ., Austin, TX, USA
pp. 115-119

Frequency interleaving as a codesign scheduling paradigm (Abstract)

J.M. Paul , Center for Electron. Design Autom., Carnegie Mellon Univ., Pittsburgh, PA, USA
pp. 131-135

Automatic test bench generation for simulation-based validation (PDF)

M. Lajolo , C&C Res. Labs., NEC Res. Inst., Princeton, NJ, USA
pp. 136-140

A novel codesign methodology for real-time embedded COTS multiprocessor-based signal processing systems (Abstract)

R.S. Janka , Georgia Tech. Res. Inst., Georgia Inst. of Technol., Atlanta, GA, USA
pp. 157-161
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