The Community for Technology Leaders
Proceedings Sixth International Symposium on High-Performance Computer Architecture. HPCA-6 (Cat. No.PR00550) (2000)
Toulouse, France
Jan. 8, 2000 to Jan. 12, 2000
ISBN: 0-7695-0550-3

List of Referees (PDF)

pp. xii
Keynote Address I
Session 1: System Architecture Tradeoffs

Impact of Chip-Level Integration on Performance of OLTP Workloads (Abstract)

Luiz Andre Barroso , Compaq Computer Corporation
Kourosh Gharachorloo , Compaq Computer Corporation
Andreas Nowatzyk , Compaq Computer Corporation
Ben Verghese , Compaq Computer Corporation
pp. 3

Toward A Cost-Effective DSM Organization that Exploits Processor-Memory Integration (Abstract)

Josep Torrellas , University of Illinois at Urbana-Champaign
Anthony-Trung Nguyen , University of Illinois at Urbana-Champaign
Liuxi Yang , Sun Microsystems
pp. 15

Impact of Heterogeneity on DSM Performance (Abstract)

Renato J.O. Figueiredo , Purdue University
Jose A.B. Fortes , Purdue University
pp. 26
Session 2a: Memory and Cache

Design of a Parallel Vector Access Unit for SDRAM Memory Systems (Abstract)

Binu K. Mathew , University of Utah
Sally A. McKee , University of Utah
John B. Carter , University of Utah
Al Davis , University of Utah
pp. 39

Modified LRU Policies for Improving Second-Level Cache Behavior (Abstract)

Wayne A. Wong , University of Washington
Jean-Loup Baer , University of Washington
pp. 49

eXtended Block Cache (Abstract)

Stephan Jourdan , Intel Corporation
Lihu Rappoport , Intel Corporation
Yoav Almog , Intel Corporation
Mattan Erez , Intel Corporation
Adi Yoaz , Intel Corporation
Ronny Ronen , Intel Corporation
pp. 61
Session 2b: Networks

Flit-Reservation Flow Control (Abstract)

Li-Shiuan Peh , Stanford University
William J. Dally , Stanford University
pp. 73

Performance Evaluation of Dynamic Reconfiguration in High-Speed Local Area Networks (Abstract)

Rafael Casado , Universidad de Castilla-La Mancha
Aurelio Bermúdez , Universidad de Castilla-La Mancha
Francisco J. Quiles , Universidad de Castilla-La Mancha
José L. Sánchez , Universidad de Castilla-La Mancha
José Duato , Universidad Polit?cnica de Valencia
pp. 85

Investigating QoS Support for Traffic Mixes with the MediaWorm Router (Abstract)

Ki Hwan Yum , Pennsylvania State University
Aniruddha Vaidya , Pennsylvania State University
Chita R. Das , Pennsylvania State University
Anand Sivasubramaniam , Pennsylvania State University
pp. 97
Session 3a: Multithreading and Microarchitecture

Quantifying the SMT Layout Overhead-Does SMT Pull Its Weight? (Abstract)

James Burns , TRW and University of Southern California
Jean-Luc Gaudiot , University of Southern California
pp. 109

Software-Controlled Multithreading Using Informing Memory Operations (Abstract)

Todd C. Mowry , Carnegie Mellon University
Sherwyn R. Ramkissoon , University of Toronto
pp. 121

Dynamic Cluster Assignment Mechanisms (Abstract)

Ramon Canal , Universitat Politecnica de Catalunya
Joan Manuel Parcerisa , Universitat Politecnica de Catalunya
Antonio Gonzalez , Universitat Politecnica de Catalunya
pp. 133
Session 3b: Shared Memory

High-Throughput Coherence Controllers (Abstract)

Anthony-Trung Nguyen , University of Illinois and Urbana-Champaign
Ashwini Nanda , IBM Research
Maged Michael , IBM Research
Douglas Joseph , IBM Research
pp. 145

Coherence Communication Prediction in Shared-Memory Multiprocessors (Abstract)

Stefanos Kaxiras , Bell Laboratories, Lucent Technologies
Cliff Young , Bell Laboratories, Lucent Technologies
pp. 156
Panel Session I
Keynote Address II
Session 4: Software Techniques

On the Performance of Hand vs. Automatically Optimized Numerical Codes (Abstract)

Marta Jimenez , Universitat Politecnica de Catalunya
Jose M. Llaberia , Universitat Politecnica de Catalunya
Agustin Fernandez , Universitat Politecnica de Catalunya
pp. 183

Cache-Efficient Matrix Transposition (Abstract)

Siddhartha Chatterjee , University of North Carolina at Chapel Hill
Sandeep Sen , Indian Institute of Technology
pp. 195

A Prefetching Technique for Irregular Accesses to Linked Data Structures (Abstract)

Magnus Karlsson , Chalmers University of Technology
Per Stenström , Chalmers University of Technology
Fredrik Dahlgren , Ericsson Mobile Communications AB
pp. 206

Reducing Code Size with Run-Time Decompression (Abstract)

Charles Lefurgy , University of Michigan
Eva Piccininni , University of Michigan
Trevor Mudge , University of Michigan
pp. 218
Session 5a: Prediction I

Decoupled Value Prediction on Trace Processors (Abstract)

Sang-Jeong Lee , Soonchunhyang University
Yuan Wang , University of Minnesota
Pen-Chung Yew , University of Minnesota
pp. 231

Branch Transition Rate: A New Metric for Improved Branch Classification Analysis (Abstract)

Michael Haungs , University of California at Davis
Phil Sallee , University of California at Davis
Matthew Farrens , University of California at Davis
pp. 241

Combining Static and Dynamic Branch Prediction to Reduce Destructive Aliasing (Abstract)

Harish Patil , Compaq Computer Corporation
Joel Emer , Compaq Computer Corporation
pp. 251
Session 5b: Parallel Systems

The Effect of Network Total Order, Broadcast, and Remote-Write Capability on Network-Based Shared Memory Computing (Abstract)

Robert Stets , Compaq Computer Corporation
Leonidas Kontothanassis , Compaq Computer Corporation
Sandhya Dwarkadas , University of Rochester
Umit Rencuzogullari , University of Rochester
Michael L. Scott , University of Rochester
pp. 265

PowerMANNA: A Parallel Architecture Based on the PowerPC MPC620 (Abstract)

P.M. Behr , GMD - German National Research Center for Information Technology
S. Pletner , GMD - German National Research Center for Information Technology
A.C. Sodan , University of New Mexico
pp. 277

A DSM Architecture for a Parallel Computer Cenju-4 (Abstract)

Takeo Hosomi , NEC Corporation
Yasushi Kanoh , NEC Corporation
Masaaki Nakamura , NEC Corporation
Tetsuya Hirose , NEC Corporation
pp. 287
Session 6a: Prediction II

Trace Cache Redundancy: Red & Blue Traces (Abstract)

Alex Ramirez , Universitat Politecnica de Catalunya
Josep L. Larriba-Pey , Universitat Politecnica de Catalunya
Mateo Valero , Universitat Politecnica de Catalunya
pp. 325
Session 6b: Parallel Systems Performance

Evaluation of Active Disks for Decision Support Databases (Abstract)

Mustafa Uysal , University of Maryland at College Park
Joel Saltz , University of Maryland at College Park
Anurag Acharya , University of California at Santa Barbara
pp. 337

Investigating the Performance of Two Programming Models for Clusters of SMP PCs (Abstract)

Franck Cappello , Universite Paris-Sud
Olivier Richard , Universite Paris-Sud
Daniel Etiemble , Universite Paris-Sud
pp. 349

Performance Analysis and Visualization of Parallel Systems Using SimOS and Rivet: A Case Study (Abstract)

Robert Bosch , Stanford University
Chris Stolte , Stanford University
Gordon Stoll , Stanford University
Mendel Rosenblum , Stanford University
Pat Hanrahan , Stanford University
pp. 360
Special Session
Keynote Address III
Session 7: Novel Architecture Issues

Register Organization for Media Processing (Abstract)

Scott Rixner , Stanford University and Massachusetts Institute of Technology
William J. Dally , Stanford University
Brucek Khailany , Stanford University
Peter Mattson , Stanford University
Ujval J. Kapasi , Stanford University
John D. Owens , Stanford University
pp. 375

Architectural Issues in Java Runtime Systems (Abstract)

R. Radhakrishnan , University of Texas at Austin
L.K. John , University of Texas at Austin
N. Vijaykrishnan , Pennsylvania State University
A. Sivasubramaniam , Pennsylvania State University
pp. 387

The Best Distribution for a Parallel OpenGL 3D Engine with Texture Caches (Abstract)

Alexis Vartanian , Universite Paris-Sud
Jean-Luc Bechennec , Universite Paris-Sud
Nathalie Drach-Temam , Universite Paris-Sud
pp. 399

Cache Memory Design for Network Processors (Abstract)

Tzi-Cker Chiueh , State University of New York at Stony Brook
Prashant Pradhan , State University of New York at Stony Brook
pp. 409
Workshop Overviews

Author Index (PDF)

pp. 419
98 ms
(Ver 3.3 (11022016))