HOT Interconnects 9 - 2001 [front matter] (PDF)
Message from the General Chair (PDF)
Message from the Technical Program Chairs (PDF)
Executive Committee (PDF)
Program Committee (PDF)
An Efficient Randomized Algorithm for Input-Queued Switch Scheduling (Abstract)
An Implementable Parallel Scheduler for Input-Queued Switches (Abstract)
OC-3072 Packet Classification Using BDDs and Pipelined SRAMs (Abstract)
Synfinity II-A High-Speed Interconnect with 2GBytes/sec Self-Configurable Physical Link (Abstract)
Optical-Interconnection as an IP Macro of a CMOS Library (Abstract)
The Sun Fireplane SMP Interconnect in the Sun Fire 3800-6800 (Abstract)
TCP Switching: Exposing Circuits to IP (Abstract)
Stonehenge: A Fault-Tolerant Real-Time Network-Attached Storage Device (Abstract)
High-Speed, High-Bandwidth DRAM Memory Bus with Crosstalk Transfer Logic (XTL) Interface (Abstract)
The Future of MPLS (PDF)
Deferred Segmentation for Wire-Speed Transmission of Large TCP Frames over Standard GbE Networks (Abstract)
Evaluation of SCSI over TCP/IP and SCSI over Fibre Channel Connections (Abstract)
Layered Protocol Wrappers for Internet Packet Processing in Reconfigurable Hardware (Abstract)
Quality of Service Guarantee on 802.11 Networks (Abstract)
Analysis of a Statistics Counter Architecture (Abstract)
The Alpha 21364 Network Architecture (Abstract)
RHiNET-3/SW: An 80-Gbit/s High-Speed Network Switch for Distributed Parallel Computing (Abstract)
The Quadrics Network (QsNet): High-Performance Clustering Technology (Abstract)
On the Techniques of Clock Extraction and Oversampling (Abstract)
New World Campus Networking (Abstract)
Author Index (PDF)
