[Front matter] (PDF)
Robust privacy-preserving fingerprint authentication (Abstract)
UCR: An unclonable chipless RFID tag (Abstract)
A highly reliable and tamper-resistant RRAM PUF: Design and experimental validation (Abstract)
Machine learning resistant strong PUF: Possible or a pipe dream? (Abstract)
LEDPUF: Stability-guaranteed physical unclonable functions through locally enhanced defectivity (Abstract)
Parsimonious design strategy for linear layers with high diffusion in block ciphers (Abstract)
Iterating Von Neumann's post-processing under hardware constraints (Abstract)
Controlling your control flow graph (Abstract)
An area-optimized serial implementation of ICEPOLE authenticated encryption schemes (Abstract)
Round gating for low energy block ciphers (Abstract)
Functional polymorphism for intellectual property protection (Abstract)
The Conjoined Microprocessor (Abstract)
Low-area hardware implementations of CLOC, SILC and AES-OTR (Abstract)
Functional block identification in circuit design recovery (Abstract)
Robust hardware true random number generators using DRAM remanence effects (Abstract)
Blinded random corruption attacks (Abstract)
Trust games: How game theory can guide the development of hardware Trojan detection methods (Abstract)
ACBuilder: A tool for hardware architecture security evaluation (Abstract)
On the problems of realizing reliable and efficient ring oscillator PUFs on FPGAs (Abstract)
Model checking to find vulnerabilities in an instruction set architecture (Abstract)
SDSM: Fast and scalable security support for directory-based distributed shared memory (Abstract)
Adaptive real-time Trojan detection framework through machine learning (Abstract)
Scalable SoC trust verification using integrated theorem proving and model checking (Abstract)
Information leakage behind the curtain: Abusing anti-EMI features for covert communication (Abstract)
Granularity and detection capability of an adaptive embedded Hardware Trojan detection system (Abstract)
Electronic forensic techniques for manufacturer attribution (Abstract)
A layout-driven framework to assess vulnerability of ICs to microprobing attacks (Abstract)
A new approach for rowhammer attacks (Abstract)
Hardware-based workload forensics: Process reconstruction via TLB monitoring (Abstract)
A key-centric processor architecture for secure computing (Abstract)
Hardware security risk assessment: A case study (Abstract)
A zero-cost approach to detect recycled SoC chips using embedded SRAM (Abstract)
Redirecting DRAM memory pages: Examining the threat of system memory Hardware Trojans (Abstract)
Large laser spots and fault sensitivity analysis (Abstract)
The other side of the coin: Analyzing software encoding schemes against fault injection attacks (Abstract)
IP core protection using voltage-controlled side-channel receivers (Abstract)
A separation and protection scheme for on-chip memory blocks in FPGAs (Abstract)
A secure camouflaged threshold voltage defined logic family (Abstract)
SARLock: SAT attack resistant logic locking (Abstract)
Template attacks using classification algorithms (Abstract)
GenMatch: Secure DNA compatibility testing (Abstract)