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2017 IEEE International High Level Design Validation and Test Workshop (HLDVT) (2017)
Santa Cruz, CA, USA
Oct. 5, 2017 to Oct. 6, 2017
ISSN: 2471-7827
ISBN: 978-1-5090-3998-2
TABLE OF CONTENTS

Author index (PDF)

pp. 1-2

A randomized algorithm for constructing cross-feature tests from single feature tests (Abstract)

Guy Barash , SanDisk, a Western Digital brand - Israel
Eitan Farchi , IBM Research - Israel
pp. 1-8

Reachability analysis in RTL circuits using k-induction bounded model checking (Abstract)

Tonmoy Roy , Bradley Department of Electrical and Computer Engineering, Virginia Polytechnic Institute and State University, Blacksburg, Virginia
Michael Hsiao , Bradley Department of Electrical and Computer Engineering, Virginia Polytechnic Institute and State University, Blacksburg, Virginia
pp. 9-16

A novel SAT-based ATPG approach for transition delay faults (Abstract)

Farzaneh Zokaee , School of Electrical and Computer Engineering, University of Tehran, Tehran, Iran
Hossein Sabaghian-Bidgoli , Department of Computer Engineering, University of Kashan, Kashan, Iran
Vahid Janfaza , School of Electrical and Computer Engineering, University of Tehran, Tehran, Iran
Payman Behnam , School of Electrical and Computer Engineering, University of Tehran, Tehran, Iran
Zainalabedin Navabi , School of Electrical and Computer Engineering, University of Tehran, Tehran, Iran
pp. 17-22

Validation of HMI applications for industrial smart display (Abstract)

Michele Lora , Department of Computer Science, University of Verona, Italy
pp. 23-30

HES machine: Harmonic equivalent state machine modeling for cyber-physical systems (Abstract)

Maral Amir , Donald Bren School of Information and Computer Sciences, CS Department, University of California, Irvine, California, USA
Tony Givargis , Donald Bren School of Information and Computer Sciences, CS Department, University of California, Irvine, California, USA
pp. 31-38

Designing cyber-physical systems from natural language descriptions (Abstract)

Sophia Balkovski , Department of Computer Science, University of California Irvine
Ian G. Harris , Department of Computer Science, University of California Irvine
pp. 39-44

Automated test generation for post silicon microcontroller validation (Abstract)

Pankaj Moharikar , Automotive Microcontroller, Infineon Technologies, Bangalore, India
Jayakrishna Guddeti , Automotive Microcontroller, Infineon Technologies, Bangalore, India
pp. 45-52

Repair techniques for aged TSVs in 3D integrated circuits (Abstract)

Siroos Madani , The Center for Advanced Computer Studies (CACS), University of Louisiana at Lafayette, Lafayette, USA
Kasem Khalil , The Center for Advanced Computer Studies (CACS), University of Louisiana at Lafayette, Lafayette, USA
Bappaditya Dey , The Center for Advanced Computer Studies (CACS), University of Louisiana at Lafayette, Lafayette, USA
Devante Bonton , The Center for Advanced Computer Studies (CACS), University of Louisiana at Lafayette, Lafayette, USA
Magdy Bayoumi , The Center for Advanced Computer Studies (CACS), University of Louisiana at Lafayette, Lafayette, USA
pp. 53-58

RTL level trace signal selection and coverage estimation during post-silicon validation (Abstract)

Binod Kumar , Indian Institute of Technology Bombay, India
Kanad Basu , New York University, USA
Masahiro Fujita , University of Tokyo, Japan
Virendra Singh , Indian Institute of Technology Bombay, India
pp. 59-66

Exploiting sub-graph isomorphism and probabilistic neural networks for the detection of hardware Trojans at RTL (Abstract)

Florenc Demrozi , Department of Computer Science, University of Verona, Italy
Riccardo Zucchelli , Department of Computer Science, University of Verona, Italy
Graziano Pravadelli , Department of Computer Science, University of Verona, Italy
pp. 67-73

Thread- and data-level parallel simulation in SystemC, a Bitcoin miner case study (Abstract)

Zhongqi Cheng , Center for Embedded and Cyber-Physical Systems, University of California, Irvine, USA
Tim Schmidt , Center for Embedded and Cyber-Physical Systems, University of California, Irvine, USA
Guantao Liu , Center for Embedded and Cyber-Physical Systems, University of California, Irvine, USA
Rainer Doomer , Center for Embedded and Cyber-Physical Systems, University of California, Irvine, USA
pp. 74-81

Design and implementation of FPGA-based muscle conduction velocity tracker in dynamic contractions during the gait (Abstract)

D. De Venuto , Dept. of Electrical and Information Engineering (DEI), Politecnico di Bari, Italy
G. Mezzina , Dept. of Electrical and Information Engineering (DEI), Politecnico di Bari, Italy
V. L. Gallo , Dept. of Electrical and Information Engineering (DEI), Politecnico di Bari, Italy
pp. 82-86

3D-DyCAC: Dynamic numerical-based mechanism for reducing crosstalk faults in 3D ICs (Abstract)

Zahra Shirmohammadi , School of Computer Science, Institute for Research in Fundamental Sciences (IPM)
Hadi Zamani Sabzi , University of California Riverside
Seyed Ghassem Miremadi , Sharif University of Technology
pp. 87-90

On generation of properties from specification (Abstract)

Keerthikumara Devarajegowda , Infineon Technologies AG
Wolfgang Ecker , Infineon Technologies AG
pp. 95-98
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