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Proceedings of the Twenty-Seventh Annual Hawaii International Conference on System Sciences (1994)
Wailea, HI, USA
Jan. 4, 1994 to Jan. 7, 1994
ISBN: 0-8186-5090-7
TABLE OF CONTENTS

Fast locks in distributed shared memory systems (PDF)

G. Hermannsson , SUNY, Stony Brook, NY, USA
L. Wittie , SUNY, Stony Brook, NY, USA
pp. 574-583

Adding fault-tolerance to algorithms for weak consistency (PDF)

S.F. Hummel , Dept. of Comput. Sci., Polytechnic Univ., Brooklyn, NY, USA
pp. 564-573

Locating multiprocessor TLBs at memory (PDF)

P.J. Teller , Dept. of Comput. Sci., New Mexico State Univ., Las Cruces, NM, USA
pp. 554-563

Interleaved dual tag directory scheme for cache coherence (PDF)

M. Thapar , Res. Labs., Hewlett-Packard Co., Palo Alto, CA, USA
pp. 546-553

Simple COMA node implementations (PDF)

E. Hagersten , Sun Microsyst. Comput. Corp., Mountain View, CA, USA
pp. 522-533

Scalable shared-memory architectures. Introduction to the minitrack (PDF)

P. Stenstrom , Dept. of Comput. Sci., Lund Univ., Sweden
pp. 520-521

Time-division optical micro-area networks (PDF)

P.R. Prucnal , Dept. of Electr. Eng., Princeton Univ., NJ, USA
pp. 509-518

Optical interconnects for multiprocessor architectures using wavelength-division multiplexing (PDF)

M. Borella , Dept. of Comput. Sci., California Univ., Davis, CA, USA
B. Mukherjee , Dept. of Comput. Sci., California Univ., Davis, CA, USA
F. Jia , Dept. of Comput. Sci., California Univ., Davis, CA, USA
S. Ramamurthy , Dept. of Comput. Sci., California Univ., Davis, CA, USA
D. Banerjee , Dept. of Comput. Sci., California Univ., Davis, CA, USA
J. Iness , Dept. of Comput. Sci., California Univ., Davis, CA, USA
pp. 499-508

An optical hypercube local area network (PDF)

F. Reichmeyer , Dept. of Electr. & Comput. Eng., Syracuse Univ., NY, USA
S. Hariri , Dept. of Electr. & Comput. Eng., Syracuse Univ., NY, USA
W. Song , Dept. of Electr. & Comput. Eng., Syracuse Univ., NY, USA
K. Jabbour , Dept. of Electr. & Comput. Eng., Syracuse Univ., NY, USA
pp. 471-480

Memory hardware support for sparse computations (PDF)

A.J. Niessen , Dept. of Comput. Sci., Leiden Univ., Netherlands
H.A.G. Wijshoff , Dept. of Comput. Sci., Leiden Univ., Netherlands
pp. 441-450

Experimental implementation of dynamic access ordering (PDF)

S.A. McKee , Virginia Univ., Charlottesville, VA, USA
R.H. Klenke , Virginia Univ., Charlottesville, VA, USA
A.J. Schwab , Virginia Univ., Charlottesville, VA, USA
W.A. Wulf , Virginia Univ., Charlottesville, VA, USA
S.A. Moyer , Virginia Univ., Charlottesville, VA, USA
J.H. Aylor , Virginia Univ., Charlottesville, VA, USA
pp. 431-440

Performance and design choices of level-two caches (PDF)

Ju-Ho Tang , IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA
pp. 422-430

Selective victim caching: a method to improve the performance of direct-mapped caches (PDF)

D. Stiliadis , Dept. of Comput. Eng., California Univ., Santa Cruz, CA, USA
A. Varma , Dept. of Comput. Eng., California Univ., Santa Cruz, CA, USA
pp. 412-421

Improvements to the ETS dynamic dataflow architecture (PDF)

P. Patadia , Texas Univ., Arlington, TX, USA
V. Karani , Texas Univ., Arlington, TX, USA
K. Kavi , Texas Univ., Arlington, TX, USA
P. Shanmugam , Texas Univ., Arlington, TX, USA
B. Shirazi , Texas Univ., Arlington, TX, USA
pp. 378-387

Speeding-up mathematical morphology computations with special-purpose array processors (PDF)

A. Broggi , Dipartimento di Ingegneria dell'Inf., Parma Univ., Italy
pp. 321-330

A simple and scalable architecture for rapidly expandable networks (PDF)

P. Gburzynski , Dept. of Comput. Sci., Alberta Univ., Edmonton, Alta., Canada
pp. 481-490

An extended fiber-optic backplane for multiprocessors (PDF)

A.V. Ramanan , Dept. of Electr. & Comput. Eng., Colorado Univ., Boulder, CO, USA
H.F. Jordan , Dept. of Electr. & Comput. Eng., Colorado Univ., Boulder, CO, USA
J.R. Sauer , Dept. of Electr. & Comput. Eng., Colorado Univ., Boulder, CO, USA
pp. 462-470

Flash memory file caching for mobile computers (PDF)

B. Marsh , Matsushita Inf. Technol. Lab., Princeton, NJ, USA
F. Douglis , Matsushita Inf. Technol. Lab., Princeton, NJ, USA
P. Krishnan , Matsushita Inf. Technol. Lab., Princeton, NJ, USA
pp. 451-460

V++: an instruction-restructurable processor architecture (PDF)

T. Arita , Dept. of Electr. Eng. & Comput. Sci., Nagoya Inst. of Technol., Japan
H. Takagi , Dept. of Electr. Eng. & Comput. Sci., Nagoya Inst. of Technol., Japan
M. Sowa , Dept. of Electr. Eng. & Comput. Sci., Nagoya Inst. of Technol., Japan
pp. 398-407

A pipeline bubbles reduction technique for the Monsoon dataflow architecture (PDF)

Feipei Lai , Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan
pp. 388-397

Analytical modeling of multithreaded pipeline performance (PDF)

P.K. Dubey , IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA
A. Krishna , IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA
pp. 361-367

Fast evaluation of the elementary functions in double precision (PDF)

W.F. Wong , Dept. of Inf. Syst. & Comput. Sci., Nat. Univ. of Singapore, Singapore
pp. 349-358

A systolic ON-LINE non-restoring division scheme (PDF)

J.B. Andersen , Inst. of Electron. Syst., Aalborg Univ., Denmark
pp. 339-348

Radix-2 division with quotient digit prediction without prescaling (PDF)

P. Montuschi , Dipartimento di Autom. e Inf., Politecnico di Torino, Italy
L. Ciminiera , Dipartimento di Autom. e Inf., Politecnico di Torino, Italy
pp. 331-338

HASE: a flexible high performance architecture simulator (PDF)

A.R. Robertson , Dept. of Comput. Sci., Edinburgh Univ., UK
R.N. Ibbett , Dept. of Comput. Sci., Edinburgh Univ., UK
pp. 261-270

Fast accurate simulation of large shared memory multiprocessors (PDF)

B. Boothe , Dept. of Comput. Sci., Univ. of Southern Maine, Portland, ME, USA
pp. 251-260

Fast efficient simulation of write-buffer configurations (PDF)

S.G. Abraham , Dept. of Electr. Eng. & Comput. Sci., Michigan Univ., Ann Arbor, MI, USA
R.A. Sugumar , Dept. of Electr. Eng. & Comput. Sci., Michigan Univ., Ann Arbor, MI, USA
pp. 231-240

Efficient simulation methods for multi-level cache memory hierarchies (PDF)

Si-En Chang , Dept. of Inf. & Comput. Eng., Chung Yuan Christian Univ., Chung Li, Taiwan
Chia-Chang Hsu , Dept. of Inf. & Comput. Eng., Chung Yuan Christian Univ., Chung Li, Taiwan
pp. 221-230

Trace driven simulation using sampled traces (PDF)

J.W.C. Fu , Intel Corp., Folsom, CA, USA
pp. 211-220

Accelerating architectural simulation by parallel execution of trace samples (PDF)

G. Lauterbach , Sun Microsyst. Labs., Mountain View, CA, USA
pp. 205-210

Performance estimation of multistreamed, superscalar processors (PDF)

W. Yamamoto , Dept. of Electr. & Comput. Eng., California Univ., Santa Barbara, CA, USA
M.J. Serrano , Dept. of Electr. & Comput. Eng., California Univ., Santa Barbara, CA, USA
A.R. Talcott , Dept. of Electr. & Comput. Eng., California Univ., Santa Barbara, CA, USA
R.C. Wood , Dept. of Electr. & Comput. Eng., California Univ., Santa Barbara, CA, USA
M. Nemirosky , Dept. of Electr. & Comput. Eng., California Univ., Santa Barbara, CA, USA
pp. 195-204

Execution-driven simulation of a superscalar processor (PDF)

H.A. Rizvi , Dept. of Electr. & Comput. Eng., Rice Univ., Houston, TX, USA
J.B. Sinclair , Dept. of Electr. & Comput. Eng., Rice Univ., Houston, TX, USA
J.R. Jump , Dept. of Electr. & Comput. Eng., Rice Univ., Houston, TX, USA
pp. 185-194

Performance optimizations, implementation, and verification of the SGI Challenge multiprocessor (PDF)

M. Galles , Silicon Graphics Comput. Syst., Mountain View, CA, USA
E. Williams , Silicon Graphics Comput. Syst., Mountain View, CA, USA
pp. 134-143

Application-specific architectures for field-programmable VLSI technologies (PDF)

C.H. Gebotys , Dept. of Electr. & Comput. Eng., Waterloo Univ., Ont., Canada
pp. 124-130

Parallel architecture for universal digital signal processing (PDF)

V.K. Jain , Dept. of Electr. Eng., Univ. of South Florida, Tampa, FL, USA
pp. 114-123

Flexible parallel FPGA-based architectures with ArMen (PDF)

J. Champeau , Univ. de Bretagne Occidentale, Brest, France
L. Le Pape , Univ. de Bretagne Occidentale, Brest, France
B. Pottier , Univ. de Bretagne Occidentale, Brest, France
S. Rubini , Univ. de Bretagne Occidentale, Brest, France
pp. 105-113

The MGAP: a high performance, user programmable, multifunctional architecture for DSP (PDF)

M. Borah , Dept. of Comput. Sci., Pennsylvania State Univ., University Park, PA, USA
C. Nagendra , Dept. of Comput. Sci., Pennsylvania State Univ., University Park, PA, USA
M.J. Irwin , Dept. of Comput. Sci., Pennsylvania State Univ., University Park, PA, USA
R. Owens , Dept. of Comput. Sci., Pennsylvania State Univ., University Park, PA, USA
pp. 96-104

Fixpt: a C++ method for development of fixed point digital signal processing algorithms (PDF)

W. Cammack , Integrated Syst. Lab., Texas Instrum. Inc., Dallas, TX, USA
M. Paley , Integrated Syst. Lab., Texas Instrum. Inc., Dallas, TX, USA
pp. 87-95

A design methodology for the conceptual design of application specific digital processors in mechatronic systems (PDF)

H.-J. Herpel , Inst. for Microelectron. Syst., Darmstadt Univ. of Technol., Germany
M. Held , Inst. for Microelectron. Syst., Darmstadt Univ. of Technol., Germany
M. Glesner , Inst. for Microelectron. Syst., Darmstadt Univ. of Technol., Germany
pp. 78-86

A comparative study of multiprocessor list scheduling heuristics (PDF)

G. Liao , Dept. of Electr. Eng., McGill Univ., Montreal, Que., Canada
E.R. Altman , Dept. of Electr. Eng., McGill Univ., Montreal, Que., Canada
V.K. Agarwal , Dept. of Electr. Eng., McGill Univ., Montreal, Que., Canada
pp. 68-77

Using regular array methods for DSP module synthesis (PDF)

W. Burleson , Dept. of Electr. & Comput. Eng., Massachusetts Univ., Amherst, MA, USA
pp. 58-67

Parallel 3-D MOSFET simulation (PDF)

B. Bagheri , TCAMC, Houston Univ., TX, USA
A. Ilin , TCAMC, Houston Univ., TX, USA
L.R. Scott , TCAMC, Houston Univ., TX, USA
pp. 46-54

An algorithm for area and delay optimisation of sequential machines through decomposition (PDF)

A. Dasgupta , Dept. of Electr. & Comput. Eng., Massachusetts Univ., Amherst, MA, USA
I. Koren , Dept. of Electr. & Comput. Eng., Massachusetts Univ., Amherst, MA, USA
pp. 36-45

High-speed circuit design: CAD tools and computational challenges (PDF)

B.L. Hutchings , Dept. of Electr. & Comput. Eng., Brigham Young Univ., Provo, UT, USA
pp. 26-35

Parallel implementation of BDD algorithms using a distributed shared memory (PDF)

Y. Parasuram , Dept. of Electr. & Comput. Eng., Syracuse Univ., NY, USA
E. Stabler , Dept. of Electr. & Comput. Eng., Syracuse Univ., NY, USA
Shiu-Kai Chin , Dept. of Electr. & Comput. Eng., Syracuse Univ., NY, USA
pp. 16-25

Computational challenges in simulations of ULSI semiconductor devices (PDF)

R.K. Smith , AT&T Bell Labs., Murray Hill, NJ, USA
W.M. Coughran , AT&T Bell Labs., Murray Hill, NJ, USA
pp. 7-15

Minitrack on computer design: a new grand challenge (PDF)

L.R. Scott , Dept. of Math., Houston Univ., TX, USA
pp. 3-6
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