The Community for Technology Leaders
Twenty-Third Annual Hawaii International Conference on System Sciences (1990)
Kailua-Kona, HI, USA
Jan. 2, 1990 to Jan. 5, 1990
TABLE OF CONTENTS

Methodologies for experimental research in computer architecture and performance measurement (PDF)

Y.N. Patt , Dept. of Electr. Eng. & Comput. Sci., Michigan Univ., Ann Arbor, MI, USA
pp. 2-5 vol.1

Benchmark characterization for experimental system evaluation (PDF)

T.M. Conte , Center for Reliable & High-performance Comput., Illinois Univ., Urbana, IL, USA
W.-m.W. Hwu , Center for Reliable & High-performance Comput., Illinois Univ., Urbana, IL, USA
pp. 6-18 vol.1

Implementation of the epsilon psilon dataflow processor (PDF)

V.G. Grafe , Sandia Nat. Lab., Albuquerque, NM, USA
J.E. Hoch , Sandia Nat. Lab., Albuquerque, NM, USA
pp. 19-29 vol.1

Analysis of experimental Prolog-database hardware (PDF)

I. Gibson , Dept. of Comput. Sci., New South Wales Univ., Kensington, NSW, Australia
pp. 30-39 vol.1

B-HIVE: hardware and software for an experimental multiprocessor (PDF)

D.P. Agrawal , North Carolina State Univ., Raleigh, NC, USA
W.E. Alexander , North Carolina State Univ., Raleigh, NC, USA
E.F. Gehringer , North Carolina State Univ., Raleigh, NC, USA
J. Mauney , North Carolina State Univ., Raleigh, NC, USA
T.K. Miller , North Carolina State Univ., Raleigh, NC, USA
pp. 40-47

Software primitives for emulation of multiprocessor architectures (PDF)

A. Svensson , Dept. of Comput. Eng., Lund Univ., Sweden
pp. 48-56 vol.1

Comparison and evaluation of two catalytic migration approaches for the design of windowing-oriented register file structures (PDF)

G. Jung , Sch. of Electr. Eng., Purdue Univ., West Lafayette, IN, USA
D.G. Meyer , Sch. of Electr. Eng., Purdue Univ., West Lafayette, IN, USA
pp. 58-64 vol.1

Reducing average access time of a parallel memory in a database environment by data permutation (PDF)

P.T. Hulina , Dept. of Electr. & Comput. Eng., Pennsylvania State Univ., University Park, PA, USA
A.R. Hurson , Dept. of Electr. & Comput. Eng., Pennsylvania State Univ., University Park, PA, USA
pp. 65-71 vol.1

Allocating processing power to minimize time costs in parallel software systems (PDF)

B. Qin , Dept. of Comput. Sci., Brandeis Univ., Waltham, MA, USA
pp. 72-81 vol.1

Parallel Astar search on message-passing architectures (PDF)

Z. Cvetanovic , Digital Equipment Corp., Boxborough, MA, USA
C. Nofsinger , Digital Equipment Corp., Boxborough, MA, USA
pp. 82-90 vol.1

Reconfiguring embedded task graphs in faulty hypercubes by automorphisms (PDF)

S.-B. Tien , Electr. Eng.-Syst., Univ. of Southern California, Los Angeles, CA, USA
C.S. Raghavendra , Electr. Eng.-Syst., Univ. of Southern California, Los Angeles, CA, USA
pp. 91-100 vol.1

An analysis of a fault tolerant scheme for processor ensembles (PDF)

S.J. Upadhyaya , Dept. of Electr. & Comput. Eng., State Univ. of New York, Buffalo, NY, USA
pp. 101-110 vol.1

Hazard prevention in combinational circuits (PDF)

P.C. McGeer , Dept. of Comput. Sci., British Columbia Univ., Vancouver, BC, Canada
pp. 111-120 vol.1

A preliminary version of an optical data-flow architecture (PDF)

A. Louri , Dept. of Electr. & Comput. Eng., Arizona Univ., Tucson, AZ, USA
pp. 121-130 vol.1

Neural networks and related emerging technologies (PDF)

O.K. Ersoy , Sch. of Electr. Eng., Purdue Univ., West Lafayette, IN, USA
pp. 131 vol.1

Speaker-independent vowel recognition: comparison of backpropagation and trained classification trees (PDF)

R.A. Cole , Dept. of Comput. Sci. & Eng., Oregon Graduate Center, Beaverton, OR, USA
Y.K. Muthusamy , Dept. of Comput. Sci. & Eng., Oregon Graduate Center, Beaverton, OR, USA
pp. 132-141 vol.1

An approach for solving the parameters setting problem (PDF)

K. Fleischer , California Inst. of Technol., Pasadena, CA, USA
J. Platt , California Inst. of Technol., Pasadena, CA, USA
A. Barr , California Inst. of Technol., Pasadena, CA, USA
pp. 151-157 vol.1

Parallel, self-organizing hierarchical neural networks (PDF)

O.K. Ersoy , Sch. of Electr. Eng., Purdue Univ., West Lafayette, IN, USA
D. Hong , Sch. of Electr. Eng., Purdue Univ., West Lafayette, IN, USA
pp. 158-169 vol.1

Nonlinear mapping with minimal supervised learning (PDF)

V.V. Tolat , Dept. of Electr. Eng., Stanford Univ., CA, USA
A.M. Peterson , Dept. of Electr. Eng., Stanford Univ., CA, USA
pp. 170-179 vol.1

Mapping of neural networks on honeycomb architectures: area analysis (PDF)

V. Milutinovic , Sch. of Electr. Eng., Belgrade Univ., Yugoslavia
pp. 180-186 vol.1

The self organizing neural network algorithm: adapting structure for optimum supervised learning (PDF)

M.F. da M. Tenorio , Sch. of Electr. Eng., Purdue Univ., West Lafayette, IN, USA
pp. 187-195 vol.1

A self-organization architecture for clustering analysis (PDF)

F.Y. Shih , Dept. of Comput. & Inf. Sci., New Jersey Inst. of Technol., Newark, NJ, USA
J. Moh , Dept. of Comput. & Inf. Sci., New Jersey Inst. of Technol., Newark, NJ, USA
pp. 196-201 vol.1

CAPS: a connectionist architecture for production systems (PDF)

A.S. Bhogal , Dept. of Electr. Eng., Waterloo Univ., Ont., Canada
R.E. Seviora , Dept. of Electr. Eng., Waterloo Univ., Ont., Canada
M.I. Elmasry , Dept. of Electr. Eng., Waterloo Univ., Ont., Canada
pp. 202-211 vol.1

Should I add a processor? (performance evaluation) (PDF)

K.S. Trivedi , Dept. of Comput. Sci., Duke Univ., Durham, NC, USA
pp. 214-221 vol.1

Performance analysis of stochastic timed Petri nets (PDF)

R.P. Wiley , Lab. for Inf. & Decision Syst., MIT, Cambridge, MA, USA
R.R. Tenney , Lab. for Inf. & Decision Syst., MIT, Cambridge, MA, USA
pp. 222-231 vol.1

A geometric model for multiple processor performance analysis (PDF)

N. Ullah , Dept. of Electr. & Compound. Eng., Texas Univ., Austin, TX, USA
M.J. Gonzalez , Dept. of Electr. & Compound. Eng., Texas Univ., Austin, TX, USA
pp. 232-241 vol.1

Simulation of parallel computer systems on a shared memory multiprocessor (PDF)

R. Mukherjee , Dept. of Electr. & Comput. Eng., Rice Univ., Houston, TX, USA
J. Bennett , Dept. of Electr. & Comput. Eng., Rice Univ., Houston, TX, USA
pp. 242-251 vol.1

Multiprocessor cache simulation using hardware collected address traces (PDF)

A.W. Wilson , Encore Comput. Corp., Marlborough, MA, USA
pp. 252-260 vol.1

Performance considerations for parallel FFT algorithms (PDF)

M. Kosaka , Carnegie Mellon Univ., Pittsburgh, PA, USA
Z. Segall , Carnegie Mellon Univ., Pittsburgh, PA, USA
pp. 261-267 vol.1

Performance analysis of high-speed computers in scientific/engineering environments (PDF)

J. Helin , Tampere Univ. of Technol., Finland
K. Kaski , Tampere Univ. of Technol., Finland
pp. 268-277 vol.1

Performance evaluation of a realtime fault tolerant distributed system (PDF)

L.S. Alger , Charles Stark Draper Lab., Cambridge, MA, USA
J.H. Lala , Charles Stark Draper Lab., Cambridge, MA, USA
pp. 278-287 vol.1

The effects of memory latency and fine-grain parallelism on Astronautics ZS-1 performance (PDF)

W. Mangione-Smith , Dept. of Electr. Eng. & Comput. Sci., Michigan Univ., Ann Arbor, MI, USA
S.G. Abraham , Dept. of Electr. Eng. & Comput. Sci., Michigan Univ., Ann Arbor, MI, USA
E.S. Davidson , Dept. of Electr. Eng. & Comput. Sci., Michigan Univ., Ann Arbor, MI, USA
pp. 288-296 vol.1

Performance monitoring on a shared-memory multiprocessor (PDF)

Z. Aral , Encore Comput. Corp., Marlborough, MA, USA
I. Gertner , Encore Comput. Corp., Marlborough, MA, USA
J. Grier , Encore Comput. Corp., Marlborough, MA, USA
G. Schaffer , Encore Comput. Corp., Marlborough, MA, USA
pp. 297-306 vol.1

Presentation tools for performance visualization: the M31 instrumentation experience (PDF)

M. Reilly , Digital Equipment Corp., Andover, MA, USA
pp. 307-313 vol.1

Performance evaluation and modeling for dynamic routing in direct multicomputer networks (PDF)

M. Ben-Ayed , Dept. of Electr. Eng., Rochester Univ., NY, USA
C.W. Merriam , Dept. of Electr. Eng., Rochester Univ., NY, USA
pp. 328-336 vol.1

Performance analysis of remote database access (PDF)

P. Krishnamurthy , Bell Commun. Res., Piscataway, NJ, USA
pp. 337-346 vol.1

Path-based scheduling for synthesis (PDF)

R. Composano , IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA
pp. 348-355 vol.1

Timing optimization of multi-phase sequential logic (PDF)

K. Bartlett , Dept. of Comput. Sci. & Eng., Washington Univ., Seattle, WA, USA
G. Borriello , Dept. of Comput. Sci. & Eng., Washington Univ., Seattle, WA, USA
S. Raju , Dept. of Comput. Sci. & Eng., Washington Univ., Seattle, WA, USA
pp. 356-366 vol.1

MUSE: a multilevel symbolic encoding algorithm for state assignment (PDF)

X. Du , Dept. of Electr. & Comput. Eng., Colorado Univ., Boulder, CO, USA
G. Hachtel , Dept. of Electr. & Comput. Eng., Colorado Univ., Boulder, CO, USA
P. Moceyunas , Dept. of Electr. & Comput. Eng., Colorado Univ., Boulder, CO, USA
pp. 367-376 vol.1

On the relationship between input encoding and logic minimization (PDF)

S. Yang , Dept. of Electr. & Comput. Eng., Massachusetts Univ., Amherst, MA, USA
M.J. Ciesielski , Dept. of Electr. & Comput. Eng., Massachusetts Univ., Amherst, MA, USA
pp. 377-386 vol.1

Exact algorithms for output encoding, state assignment and four-level Boolean minimization (PDF)

S. Devadas , Dept. of Electr. Eng. & Comput. Sci., MIT, Cambridge, MA, USA
pp. 387-396 vol.1

Retiming and resynthesis: optimizing sequential networks with combinational techniques (PDF)

S. Malik , Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
E.M. Sentovich , Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
R.K. Brayton , Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
A. Sangiovanni-Vincentelli , Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
pp. 397-406 vol.1

Logic transformations for synchronous logic synthesis (PDF)

G. De Micheli , Comput. Syst. Lab., Stanford Univ., CA, USA
R. Yip , Comput. Syst. Lab., Stanford Univ., CA, USA
pp. 407-416 vol.1

Irredundant sequential machines via optimal logic synthesis (PDF)

S. Devadas , Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
H.-K.T. Ma , Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
A.R. Newton , Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
A. Sangiovanni-Vincentelli , Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
pp. 417-426 vol.1

A unified approach to the synthesis of fully testable sequential machines (PDF)

S. Devadas , Dept. of Electr. Eng. & Comput. Sci., MIT, Cambridge, MA, USA
pp. 427-435 vol.1
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