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2011 IEEE Hot Chips 23 Symposium (HCS) (2011)
Stanford, CA, USA
Aug. 17, 2011 to Aug. 19, 2011
ISBN: 978-1-4673-8877-1
TABLE OF CONTENTS

Integrated inductors with magnetic materials for on-chip power conversion (Abstract)

Donald S. Gardner , Circuits Research Lab & Future Technology Research, Intel Labs Intel Corporation
Gerhard Schrom , Circuits Research Lab & Future Technology Research, Intel Labs Intel Corporation
Fabrice Paillet , Circuits Research Lab & Future Technology Research, Intel Labs Intel Corporation
Tanay Karnik , Circuits Research Lab & Future Technology Research, Intel Labs Intel Corporation
Shekhar Borkar , Circuits Research Lab & Future Technology Research, Intel Labs Intel Corporation
pp. 1-36

Fully integrated switched-capacitor DC-DC conversion (Abstract)

Elad Alon , Berkeley Wireless Research Center, University of California, Berkeley
Hanh-Phuc Le , Berkeley Wireless Research Center, University of California, Berkeley
Seth Sanders , Berkeley Wireless Research Center, University of California, Berkeley
pp. 1-30

The Cavium 32 Core OCTEON II 68xx (Abstract)

R. E. Kessler , Cavium, Inc. Hot Chips 23 August, 2011
pp. 1-33

The Blue Gene/Q Compute chip (Abstract)

Ruud Haring , IBM BlueGene Team
pp. 1-20

High-efficient architecture of Godson-T many-core processor (Abstract)

Dongrui Fan , Advanced Micro-System Group National Key Laboratory of Computer Architecture, Institute of Computing Technology, Chinese Academy of Sciences
Hao Zhang , Advanced Micro-System Group National Key Laboratory of Computer Architecture, Institute of Computing Technology, Chinese Academy of Sciences
Da Wang , Advanced Micro-System Group National Key Laboratory of Computer Architecture, Institute of Computing Technology, Chinese Academy of Sciences
Xiaochun Ye , Advanced Micro-System Group National Key Laboratory of Computer Architecture, Institute of Computing Technology, Chinese Academy of Sciences
Fenglong Song , Advanced Micro-System Group National Key Laboratory of Computer Architecture, Institute of Computing Technology, Chinese Academy of Sciences
Junchao Zhang , Advanced Micro-System Group National Key Laboratory of Computer Architecture, Institute of Computing Technology, Chinese Academy of Sciences
Lingjun Fan , Advanced Micro-System Group National Key Laboratory of Computer Architecture, Institute of Computing Technology, Chinese Academy of Sciences
pp. 1-31

Bandwidth engine® serial memory chip breaks 2 billion accesses/sec (Abstract)

Michael J. Miller , VP Technology Innovation & Systems Applications, MoSys
pp. 1-23

Hybrid memory cube (HMC) (Abstract)

J. Thomas Pawlowski , Architecture Development Group, Micron
pp. 1-24

XMOS architecture XS1 chips (Abstract)

David May , XMOS
pp. 1-30

The world's fastest DSP core: Breaking the 100 GMAC/s barrier (Abstract)

Chris Rowen , Tensilica Inc.
Dan Nicolaescu , Tensilica Inc.
Rajiv Ravindran , Tensilica Inc.
David Heine , Tensilica Inc.
Grant Martin , Tensilica Inc.
James Kim , Tensilica Inc.
Dror Maydan , Tensilica Inc.
Nupur Andrews , Tensilica Inc.
Bill Huffman , Tensilica Inc.
Vakis Papaparaskeva , Tensilica Inc.
Shay Gal-On , Tensilica Inc.
Peter Nuth , Tensilica Inc.
Pushkar Patwardhan , Tensilica Inc.
Manish Paradkar , Tensilica Inc.
pp. 1-25

Electrons, photons, phonons, wave, bits, and industrial design: Microsoft kinect sensor: Hot chips 23 (Abstract)

Dawson Yee , Natural User Interface Hardware, Microsoft Corporation
Scott McEldowney , Natural User Interface Hardware, Microsoft Corporation
pp. 1-20

Low-power high-density 10GBASE-T ethernet transceiver (Abstract)

Ramin Shirani , Stanford University
Ramin Farjadrad , Stanford University
pp. 1-20

One billion packet per second frame processing pipeline (Abstract)

Mike Davies , Director of IC Development, Fulcrum Microsystems
pp. 1-24

The Intel® Quick Sync Video technology in the 2nd-generation Intel Core processor family (Abstract)

Hong Jiang , Intel Corporation, Hot Chips 23, Palo Alto, CA
pp. 1-23

VENICE: A compact vector processor for FPGA applications (Abstract)

Aaron Severance , University of British Columbia, Vancouver, Canada
Guy Lemieux , University of British Columbia, Vancouver, Canada
pp. 1-5

Efficient fetch mechanism by employing instruction register (Abstract)

Mochamad Asri , Tokyo Institute of Technology
pp. 1-5

Tessellation operating system: Building a real-time, responsive, high-throughput client OS for many-core architectures (Abstract)

Juan A. Colmenares , Par Lab, UC Berkeley
Sarah Bird , Par Lab, UC Berkeley
Gage Eads , Par Lab, UC Berkeley
Steven Hofmeyr , Future Technologies Group, LBNL
Albert Kim , Par Lab, UC Berkeley
Rohit Poddar , Par Lab, UC Berkeley
Hilfi Alkaff , Par Lab, UC Berkeley
Krste Asanovic , Par Lab, UC Berkeley
John Kubiatowicz , Par Lab, UC Berkeley
pp. 1

The Maven vector-thread architecture (Abstract)

Yunsup Lee , Parallel Computing Laboratory, UC Berkeley
Rimas AviZienis , Parallel Computing Laboratory, UC Berkeley
Alex Bishara , Parallel Computing Laboratory, UC Berkeley
Richard Xia , Parallel Computing Laboratory, UC Berkeley
Derek Lockhart , Computer Systems Laboratory, Cornell University
Christopher Batten , Computer Systems Laboratory, Cornell University
Krste Asanovic , Parallel Computing Laboratory, UC Berkeley
pp. 1
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