The Community for Technology Leaders
2006 IEEE Hot Chips 18 Symposium (HCS) (2006)
Stanford, CA, USA
Aug. 20, 2006 to Aug. 22, 2006
ISBN: 978-1-4673-8867-2
TABLE OF CONTENTS

Transactional memory introduction (Abstract)

Ali-Reza Adl-Tabatabai , Programming Systems Lab, Intel Corporation, USA
pp. 1-21

Software transactional memory (Abstract)

Bratin Saha , Programming Systems Lab, Intel Corporation, USA
pp. 1-22

Transactional memory implementation overview (Abstract)

Christos Kozyrakis , Computer Systems Laboratory, Stanford University, USA
pp. 1-31

Wireless in the home - opportunities and challenges (PDF)

Jan M. Rabaey , Berkeley Wireless Research Center, Department of EECS, University of California, USA
pp. 1-134

PNX8535 hybrid television processor (Abstract)

Ben Pronk , Philips Semiconductors, The Netherlands
pp. 1-22

Z-RAM® ultra-dense memory for 90nm and below (Abstract)

David E. Fisch , Innovative Silicon Inc., USA
Anant Singh , Innovative Silicon Inc., USA
Greg Popov , Innovative Silicon Inc., USA
pp. 1-35

The ultra small HDD for the mobile applications (Abstract)

Akihiko Takeo , Development Dept., Core Technology Center, Toshiba Corporation, Digital Media Network Company, Japan
Kazuhito Shimomura , Development Dept., Core Technology Center, Toshiba Corporation, Digital Media Network Company, Japan
Jun Itoh , Development Dept., Core Technology Center, Toshiba Corporation, Digital Media Network Company, Japan
pp. 1-22

The next generation 65-nm FPGA (Abstract)

Steve Douglass , Xilinx, USA
Kees Vissers , Xilinx, USA
Peter Alfke , Xilinx, USA
pp. 1-27

Research accelerator for multiple processors (Abstract)

David Patterson , Berkeley, CO-PI, USA
Arvind , MIT, USA
Krste Asanovic , MIT, USA
Derek Chiou , Texas, USA
James Hoe , CMU, USA
Christos Kozyrakis , Stanford, USA
Shih-Lien Lu , Intel, USA
Mark Oskin , Washington, USA
Jan Rabaey , Berkeley, USA
John Wawrzynek , Berkeley-PI, USA
pp. 1-42

An implementation of hardware accelerator using dynamically reconfigurable architecture (Abstract)

Takashi Yoshikawa , Toshiba R&D Center, Japan
Yutaka Yamada , Toshiba R&D Center, Japan
Shigehiro Asano , Toshiba R&D Center, Japan
pp. 1-38

The CA1024: A fully programmable system-on-chip for costeffective HDTV media processing (Abstract)

Lazar Bivolarski , Connex Technology, Inc., USA
Bogdan Mitu , Connex Technology, Inc., USA
Anand Sheel , Connex Technology, Inc., USA
Gheorghe Stefan , Connex Technology, Inc., USA
Tom Thomson , Connex Technology, Inc., USA
Dan Tomescu , Connex Technology, Inc., USA
pp. 1-26

Hardware and applications of AsAP: An asynchronous array of simple processors (Abstract)

Bevan Baas , VLSI Computation Lab, ECE Department, University of California, Davis, USA
Zhiyi Yu , VLSI Computation Lab, ECE Department, University of California, Davis, USA
Michael Meeuwsen , VLSI Computation Lab, ECE Department, University of California, Davis, USA
Omar Sattari , VLSI Computation Lab, ECE Department, University of California, Davis, USA
Ryan Apperson , VLSI Computation Lab, ECE Department, University of California, Davis, USA
Eric Work , VLSI Computation Lab, ECE Department, University of California, Davis, USA
Jeremy Webb , VLSI Computation Lab, ECE Department, University of California, Davis, USA
Michael Lai , VLSI Computation Lab, ECE Department, University of California, Davis, USA
Daniel Gurman , VLSI Computation Lab, ECE Department, University of California, Davis, USA
Chi Chen , VLSI Computation Lab, ECE Department, University of California, Davis, USA
Jason Cheung , VLSI Computation Lab, ECE Department, University of California, Davis, USA
Dean Truong , VLSI Computation Lab, ECE Department, University of California, Davis, USA
Tinoosh Mohsenin , VLSI Computation Lab, ECE Department, University of California, Davis, USA
pp. 1-31

Microsoft microsoft in the living room (Abstract)

Bob Brummer , Digital & Entertainment Division, USA
pp. 1-5

Who owns the living room? (Abstract)

Bill Curtis , Digital Home Architecture, USA
pp. 1-8

Who owns the living room? (Abstract)

Alan Messer , SISA, Corporate Technology Operations, Samsung Electronics, USA
pp. 1-6

Who owns the living room? (Abstract)

Glen Stone , Standards & Strategy, Sony Electronics Inc., USA
pp. 1-6

Who owns the living room? (Abstract)

Q Yamada , Kyushu Institute of Technology, Japan
pp. 1-8

Design of a reusable 1GHz, superscalar ARM processor (Abstract)

Stephen Hill , ARM - Austin Design Centre, USA
pp. 1-18

Towards optimal custom instruction processors (Abstract)

Wayne Luk , Department of Computing, Imperial College London, UK
Kubilay Atasu , Department of Computing, Imperial College London, UK
Rob Dimond , Department of Computing, Imperial College London, UK
Oskar Mencer , Department of Computing, Imperial College London, UK
pp. 1-23

Collaborative innovation; a new lever in information technology development (Abstract)

Bernard Meyerson , IBM systems and technology group, Development, USA
pp. 1-27

In silico vox: Towards speech recognition in silicon (Abstract)

Edward C. Lin , Electrical & Computer Engineering, USA
Kai Yu , Electrical & Computer Engineering, USA
Rob A. Rutenbar , Electrical & Computer Engineering, USA
Tsuhan Chen , Electrical & Computer Engineering, USA
pp. 1-27

A novel processor architecture for high-performance stream processing (Abstract)

Jan van Lunteren , IBM Research GmbH, Zurich Research Laboratory, Säumerstrasse 4, CH-8803 Rüschlikon, Switzerland
pp. 1-24

Micro manipulator array for nano-bioelectronics era (Abstract)

K. Suzuki , Advanced Electron Devices Laboratory, Corporate Research and Development Center, TOSHIBA Corporation, Japan
Y. Naruse , Advanced Electron Devices Laboratory, Corporate Research and Development Center, TOSHIBA Corporation, Japan
H. Funaki , Advanced Electron Devices Laboratory, Corporate Research and Development Center, TOSHIBA Corporation, Japan
K. Itaya , Advanced Electron Devices Laboratory, Corporate Research and Development Center, TOSHIBA Corporation, Japan
S. Uchikoga , Advanced Electron Devices Laboratory, Corporate Research and Development Center, TOSHIBA Corporation, Japan
pp. 1-27

SH-MobileG1: A single-chip application and dual-mode baseband processor (Abstract)

Masayuki Ito , Renesas Technology, Japan
Takahiro Irita , Renesas Technology, Japan
Eiji Yamamoto , Renesas Technology, Japan
Kunihiko Nishiyama , Renesas Technology, Japan
Takao Koike , Renesas Technology, Japan
Yoshihiko Tsuchihashi , Renesas Technology, Japan
Hiroyuki Asano , Renesas Technology, Japan
Hiroshi Yagi , Renesas Technology, Japan
Saneaki Tamaki , Renesas Technology, Japan
Ken Tatezawa , Renesas Technology, Japan
Toshihiro Hattori , Renesas Technology, Japan
Shinichi Yoshioka , Renesas Technology, Japan
Koji Ohno , NTT DoCoMo, Japan
pp. 1-24

The APP300 access network processor (Abstract)

Balakrishnan Sundararaman , Agere Systems Inc., USA
pp. 1-29

Niagara-2: A highly threaded server-on-a-chip (Abstract)

Greg Grohoski , Sun Microsystems, USA
pp. 1-22

Blackford: A duall processor chipset for servers and workstatiions (Abstract)

Kai Cheng , Intel Corporation, USA
Sundaram Chinthamani , Intel Corporation, USA
Sivakumar Radhakrishnan , Intel Corporation, USA
Faye Briggs , Intel Corporation, USA
Kathy Debnath , Intel Corporation, USA
pp. 1-28

Inside Intel® Core microarchitecture (Abstract)

Jack Doweck , Intel® Corporation, USA
pp. 1-35
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