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2005 IEEE Hot Chips XVII Symposium (HCS) (2005)
Stanford, CA, USA
Aug. 14, 2005 to Aug. 16, 2005
ISBN: 978-1-4673-8864-1
TABLE OF CONTENTS

Committee (PDF)

pp. 1

Morning tutorials (PDF)

James E. Smith , University of Wisconsin at Madison, ECE, USA
Richard Uhlig , Intel, MRL, Oregon, USA
pp. 1

HOTCHIPS 17: Tutorial 1, part 1 (PDF)

J. E. Smith , University of Wisconsin-Madison, USA
Rich Uhlig , Intel Corporation, USA
pp. 1-152

HOTCHIPS 17: Tutorial 1, part 2 (PDF)

J. E. Smith , University of Wisconsin-Madison, USA
Rich Uhlig , Intel Corporation, USA
pp. 1-51

Circuit design for low power (PDF)

Kevin Nowka , IBM Austin Research Lab., USA
pp. 1-49

Impact of variability on power (Abstract)

Sani R. Nassif , IBM Research, Austin, USA
pp. 1-85

Welcome to hot chips 17! (PDF)

Pradeep K. Dubey , Intel Corporation, USA
pp. 1-2

From the program co-chairs of Hot Chips XVII (2005) (PDF)

Alan Jay Smith , University of California at Berkeley, USA
John Sell , Microsoft Corporation, USA
pp. 1-2

Computer history museum (Abstract)

John Mashey , Techviser, USA
pp. 1-15

Cell broadband engine interconnect and memory interface (Abstract)

Scott Clark , IBM Systems and Technology Group, Rochester, Minnesota
Kent Haselhorst , IBM Systems and Technology Group, Rochester, Minnesota
Kerry Imming , IBM Systems and Technology Group, Rochester, Minnesota
John Irish , IBM Systems and Technology Group, Rochester, Minnesota
Dave Krolak , IBM Systems and Technology Group, Rochester, Minnesota
Tolga Ozguner , IBM Systems and Technology Group, Rochester, Minnesota
pp. 1-22

Super companion chip with audio visual interface for cell processor (Abstract)

Takayuki Mihara , Toshiba Corporation, Japan
Hiroki Muroga , Toshiba Corporation, Japan
Hiroshi Doi , Toshiba Corporation, Japan
Tadashi Yabuta , Toshiba Corporation, Japan
Yoichiro Iwagami , Toshiba Corporation, Japan
Kenichi Ishii , Toshiba Corporation, Japan
Naohiko Okamoto , Toshiba Corporation, Japan
Kazuki Iwata , Toshiba Corporation, Japan
Yoshimasa Aoyama , Toshiba Corporation, Japan
Takeshi Takamiya , Toshiba Corporation, Japan
Naoki Sugawa , Toshiba Microelectronics Corporation, Japan
pp. 1-27

Programming and performance evaluation of the cell processor (Abstract)

Ryuji Sakai , Toshiba Corporation, Japan
Seiji Maeda , Toshiba Corporation, Japan
Christopher Crookes , Toshiba Corporation, Japan
Mitsuru Shimbayashi , Toshiba Corporation, Japan
Katsuhisa Yano , Toshiba Corporation, Japan
Tadashi Nakatani , Toshiba Corporation, Japan
Hirokuni Yano , Toshiba Corporation, Japan
Shigehiro Asano , Toshiba Corporation, Japan
Masaya Kato , Toshiba Corporation, Japan
Hiroshi Nozue , Toshiba Corporation, Japan
Tatsunori Kanai , Toshiba Corporation, Japan
Tomofumi Shimada , Toshiba Corporation, Japan
Koichi Awazu , Toshiba Corporation, Japan
pp. 1-26

Facing the Hot Chiip challllenge (again) (Abstract)

Bill Holt , Technology and Manufacturing Group, Inttell Corporation, Intel Corporation, USA
pp. 1-44

40-GHz operation of a single-flux-quantum (SFQ) switch scheduler (Abstract)

Y. Kameda , ISTEC, France
S. Yorozu , ISTEC, France
Y. Hashimoto , ISTEC, France
H. Terai , NICT, Japan
A. Fujimaki , Nagoya Univ., Japan
N. Yoshikawa , Yokohama National Univ., Japan
pp. 1-17

Next-generation audio engine (Abstract)

Robert Kennedy , Tensilica Inc.
Darin Petkov , Tensilica Inc.
pp. 1-19

High speed low cost nexperia PNX1700 super-pipelined media-processor (Abstract)

Luis Lucas , Philips Semiconductors, Netherlands
pp. 1-21

Low-power, networked MIMD processor for particle physics (Abstract)

Volker Lindenstruth , Kirchhoff Institute for Physics, University Heidelberg, Germany
pp. 1-34

The design and implementation of the TRIPS prototype chip (Abstract)

Robert McDonald , Computer Architecture and Technology Laboratory, Department of Computer Sciences, The University of Texas at Austin, USA
Doug Burger , Computer Architecture and Technology Laboratory, Department of Computer Sciences, The University of Texas at Austin, USA
Steve Keckler , Computer Architecture and Technology Laboratory, Department of Computer Sciences, The University of Texas at Austin, USA
pp. 1-24

Digitally assisted analog circuits (Abstract)

Boris Murmann , Stanford University, Department of Electrical Engineering, USA
pp. 1-29

A 1-GHz configurable processor core - MeP-h1 (Abstract)

Takashi Miyamori , SoC Research & Development Center, TOSHIBA Corporation, Japan
Takanori Tamai , SoC Research & Development Center, TOSHIBA Corporation, Japan
Masato Uchiyama , SoC Research & Development Center, TOSHIBA Corporation, Japan
pp. 1-25

The design and applications of BEE2: A high end reconfigurable computing system (Abstract)

Chen Chang , EECS, University of California at Berkeley, USA
John Wawrzynek , EECS, University of California at Berkeley, USA
Bob Brodersen , EECS, University of California at Berkeley, USA
pp. 1-32

TwinCastle: A multi-processor north bridge server chipset (Abstract)

Debendra Das Sharma , Advanced Components Division, Intel Corporation, USA
Ashish Gupta , Advanced Components Division, Intel Corporation, USA
Gordon Kurpanek , Advanced Components Division, Intel Corporation, USA
Dean Mulla , Advanced Components Division, Intel Corporation, USA
Bob Pflederer , Advanced Components Division, Intel Corporation, USA
Ram Rajamani , Advanced Components Division, Intel Corporation, USA
pp. 1-31

Foxton technology (Abstract)

Sam Naffziger , Intel Corp., USA
pp. 1-21

Xbox 360 system architecture (Abstract)

Jeff Andrews , Xbox Semiconductor Technology Group, Singapore
Nick Baker , Xbox Semiconductor Technology Group, Singapore
pp. 1-17
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