Proceedings of the 11th Asian Test Symposium (ATS'02) (PDF)

General Chair's Message (PDF)

Program Chair's Message (PDF)

ATS'01 Best Paper Award (PDF)

ATS Steering Committee (PDF)

Organizing Committee (PDF)

Program Committee and Voluntary Reviewers (PDF)

TTTC Activities Board (PDF)

On Generating High Quality Tests for Transition Faults (Abstract)

Exact Computation of Maximally Dominating Faults and Its Application to n-Detection Tests (Abstract)

Maximum Distance Testing (Abstract)

High Precision Result Evaluation of VLSI (Abstract)

A Totally Self-Checking Dynamic Asynchronous Datapath (Abstract)

Non-Intrusive Design of Concurrently Self-Testable FSMs (Abstract)

Test Limitations of Parametric Faults in Analog Circuits (Abstract)

Effects of Amplitude Modulation in Jitter Tolerance Measurements of Communication Devices (Abstract)

On-chip Analog Response Extraction with 1-Bit &Egr; - Δ Modulators (Abstract)

A State Reduction Method for Non-Scan Based FSM Testing with Don't Care Inputs Identification Technique (Abstract)

Improving the Efficiency of Static Compaction Based on Chronological Order Enumeration of Test Sequences (Abstract)

Test Data Compression Using Don?t-Care Identification and Statistical Encoding (Abstract)

Design for Two-Pattern Testability of Controller-Data Path Circuits (Abstract)

MD-SCAN Method for Low Power Scan Testing (Abstract)

Non-Scan Design for Testability Based on Fault Oriented Conflict Analysis (Abstract)

Specification and Design of a New Memory Fault Simulator (Abstract)

DRAM Specific Approximation of the Faulty Behavior of Cell Defects (Abstract)

An Access Timing Measurement Unit of Embedded Memory (Abstract)

A Partitioning and Storage Based Built-In Test Pattern Generation Method for Delay Faults in Scan Circuits (Abstract)

Optimal Seed Generation for Delay Fault Detection BIST (Abstract)

On-Chip Tap-Delay Measurements for a Digital Delay-Line Used in High-Speed Inter-Chip Data Communications (Abstract)

A Scheduling Method in High-Level Synthesis for Acyclic Partial Scan Design (Abstract)

Test Requirement Analysis for Low Cost Hierarchical Test Path Construction (Abstract)

Testable Realizations for ESOP Expressions of Logic Functions (Abstract)

DPSC SRAM Transparent Test Algorithm (Abstract)

Tests for Word-Oriented Content Addressable Memories (Abstract)

A High Performance IDDQ Testable Cache for Scaled CMOS Technologies (Abstract)

Enhanced Crosstalk Fault Model and Methodology to Generate Tests for Arbitrary Inter-core Interconnect Topology (Abstract)

A Testing Scheme for Crosstalk Faults Based on the Oscillation Test Signal (Abstract)

Crosstalk Fault Reduction and Simulation for Clock-Delayed Domino Circuits (Abstract)

A Concurrent Fault Simulation for Crosstalk Faults in Sequential Circuits (Abstract)

Efficient Circuit Specific Pseudoexhaustive Testing with Cellular Automata (Abstract)

Fault Set Partition for Efficient Width Compression (Abstract)

A Reseeding Technique for LFSR-Based BIST Applications (Abstract)

A ROMless LFSR Reseeding Scheme for Scan-based BIST (Abstract)

A Fault-Tolerant Architecture for Symmetric Block Ciphers (Abstract)

A New Learning Approach to Design Fault Tolerant ANNs: Finally a Zero HW-SW Overhead (Abstract)

Experimental Results of a Recovery Block Scheme to Handle Noise in Speech Recognition Systems (Abstract)

Easily Testable and Fault-Tolerant Design of FFT Butterfly Networks (Abstract)

Fault Detection and Fault Diagnosis Technoques for Lookup Table FPGA's (Abstract)

Reduction of Target Fault List for Crosstalk-Induced Delay Faults by using Layout Constraints (Abstract)

Diagnosis Of Byzantine Open-Segment Faults (Abstract)

Robust Space Compaction of Test Responses (Abstract)

An Evolutionary Strategy To Design An On-Chip Test Pattern Generator Without Prohibited Pattern Set (PPS) (Abstract)

An Embedded Built-In-Self-Test Approach for Analog-to-Digital Converters (Abstract)

Statistical Analysis of Time Series Data on the Number of Faults Detected by Statistical Analysis of Time Series Data on the Number of Faults Detected by Software Testing (Abstract)

An Analytic Software Testability Model (Abstract)

Effective Automated Testing: A Solution of Graphical Object Verification (Abstract)

At-Speed Built-in Test for Logic Circuits with Multiple Clocks (Abstract)

A Test Point Insertion Method to Reduce the Number of Test Patterns (Abstract)

A SoC Test Strategy Based on a Non-Scan DFT Method (Abstract)

Embedded Test Solution as a Breakthrough in Reducing Cost of Test for System on Chips (Abstract)

Manufacturing Test of SoCs (Abstract)

Recent Advances in Test Planning for Modular Testing of Core-Based SOCs (Abstract)

A Method to Reduce Power Dissipation during Test for Sequential Circuits (Abstract)

Test Power Optimization Techniques for CMOS Circuits (Abstract)

Reducing Test Application Time and Power Dissipation for Scan-Based Testing via Multiple Clock Disabling (Abstract)

A Simple Wrapped Core Linking Module for SoC Test Access (Abstract)

Testing System-On-Chip by Summations of Cores? Test Output Voltages (Abstract)

Test Scheduling of BISTed Memory Cores for SOC (Abstract)

Effective Error Diagnosis for RTL Designs in HDLs (Abstract)

Evolutionary Test Program Induction for Microprocessor Design Verification (Abstract)

Hierarchical Fault Simulation Using Behavioral and Gate Level Hardware Models (Abstract)

Testing Embedded Systems by Using a C++ Script Interpreter (Abstract)

Extending EDA Environment From Design to Test (Abstract)

Vector Memory Expansion System For T33xx Logic Tester (Abstract)

Integrated Test Scheduling, Test Parallelization and TAMDesign (Abstract)

Core - Clustering Based SOC Test Scheduling Optimization (Abstract)

Test Scheduling and Test Access Architecture Optimization for System-on-Chip (Abstract)

CMOS Floating Gate Defect Detection Using I _DDQ Test with DC Power Supply (Abstract)

Test Time Reduction for I _DDQ Testing by Arranging Test Vectors (Abstract)

Time Slot Specification Based Approach to Analog Fault Diagnosis Using Built-in Current Sensors and Test Point Insertion (Abstract)

Author Index (PDF)

Call for Papers of ATS'03 (PDF)