To verify manufacturing yield by testing (PDF)

Characteristics of a fuzzy test system (PDF)

A built-in self-test approach for medium to high-resolution digital-to-analog converters (PDF)

Fault diagnosis technique for subranging ADCs (PDF)

Switching networks and neural algorithms for reconstructing mesh-connected processor arrays with spares on their sides (PDF)

Design and evaluation of fault-tolerant interleaved memory systems (PDF)

A diagnostic network for massively parallel processing systems (PDF)

Experiments of faults on the "Happa" system and a proposal of backup RAM technique (PDF)

A partial scan algorithm based on reduced scan shift (PDF)

Test time reduction for scan-designed circuits by sliding compatibility (PDF)

Two techniques for minimizing power dissipation in scan circuits during test application (PDF)

Data path synthesis for easy testability (PDF)

On full path delay fault testability of combinational circuits (PDF)

Testable synthesis and testing of finite state machines (PDF)

Automatic program generator for simulation-based processor verification (PDF)

Automatic test generation for functional verification of microprocessors (PDF)

Time-space modal model checking towards verification of bit-slice architecture (PDF)

Minimum test sets for locally exhaustive testing of combinational circuits with five outputs (PDF)

Design of pseudo-random patterns with low linear dependence and equi-distribution (PDF)

A unified method for assembling global test schedules (PDF)

Design verification by using universal test sets (PDF)

Gate-level design diagnosis using a learning-based search strategy (PDF)

Boolean process-an analytical approach to circuit representation (PDF)

Evaluations of various TPG circuits for use in two-pattern testing (PDF)

Selecting programmable space compactors for BIST using genetic algorithms (PDF)

Design of random pattern testable floating point adders (PDF)

Netlist automatic extractor: "An image processing based software for bare board test data generation" (PDF)

Efficient test sequence generation for localization of multiple faults in communication protocols (PDF)

Software design verification using FTA (PDF)

Design in fault isolating of ternary cellular arrays using ternary decision diagrams (PDF)

A new testable design of logic circuits under highly observable condition (PDF)

Detectability of spurious signals with limited propagation in combinational circuits (PDF)

Analysis and improvement of testability measure approximation algorithms (PDF)

On crosstalk fault detection in hierarchical VLSI logic circuits (PDF)

A unified model for inter-gate and intra-gate CMOS bridging fault: the configuration ratio (PDF)

C-testable multipliers based on the modified Booth algorithm (PDF)

Easily testable realizations for generalized Reed-Muller expressions (PDF)

Testability considerations in technology mapping (PDF)

The effect of fault detection by IDDq measurement for CMOS VLSIs (PDF)

A built-in I/sub DDQ/ test circuit utilizing upper and lower limits (PDF)

Random test input generation for supply current testing of TTL combinational circuits (PDF)

Testing of analog integrated circuits based on power-supply current monitoring and discrimination analysis (PDF)

Sequential test generation in massive observability environments (PDF)

Efficient fault ordering for automatic test pattern generation for sequential circuits (PDF)

Test generation for redundant faults in combinational circuits by using delay effects (PDF)

A genetic approach to test generation for logic circuits (PDF)

Efficient diagnostic fault simulation for sequential circuits (PDF)

An approach of diagnosing single bridging faults in CMOS combinational circuits (PDF)

Efficiency improvements for multiple fault diagnosis of combinational circuits (PDF)

An efficient logical fault diagnosis for combinational circuits using stuck-at fault simulation (PDF)

On the performance analysis of parallel processing for test generation (PDF)

Test scheduling using test subsession partitioning (PDF)

A sequential redundant fault identification scheme and its application to test generation (PDF)

Efficient techniques for multiple fault test generation (PDF)

Strongly fail-safe interfaces based on concurrent checking (PDF)

Application of byte error detecting codes to the design of self-checking circuits (PDF)

Fault coverage analysis in monitored sequential circuits (PDF)

Bounding error masking in linear output space compression schemes (PDF)

Delay fault propagation in synchronous sequential circuits (PDF)

Fault detection by transient transition count testing (PDF)

Hardware-accelerated parallel-pattern/multiple-fault-propagation concurrent fault simulation (PDF)

Test generation and fault simulation algorithms for sequential circuits with embedded RAMs (PDF)

Proceedings of IEEE 3rd Asian Test Symposium (ATS) (PDF)