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Proceedings of IEEE 3rd Asian Test Symposium (ATS) (1994)
Nara, Japan
Nov. 15, 1994 to Nov. 17, 1994
ISBN: 0-8186-6690-0
TABLE OF CONTENTS

To verify manufacturing yield by testing (PDF)

Mill-Jer Wang , Chung-Hua Polytech. Inst., Hsinchu, Taiwan
Jwu-E Chen , Chung-Hua Polytech. Inst., Hsinchu, Taiwan
Yung-Yuan Chen , Chung-Hua Polytech. Inst., Hsinchu, Taiwan
pp. 385-390

Characteristics of a fuzzy test system (PDF)

T. Koyama , Tokushima Bunri Univ, Japan
pp. 379-384

A built-in self-test approach for medium to high-resolution digital-to-analog converters (PDF)

K. Arabi , Dept. of Electr. & Comput. Eng., Ecole Polytech. de Montreal, Que., Canada
B. Kaminska , Dept. of Electr. & Comput. Eng., Ecole Polytech. de Montreal, Que., Canada
pp. 373-378

Fault diagnosis technique for subranging ADCs (PDF)

A. Charoenrook , Dept. of Electr. Eng., Washington Univ., Seattle, WA, USA
M. Soma , Dept. of Electr. Eng., Washington Univ., Seattle, WA, USA
pp. 367-372

Design and evaluation of fault-tolerant interleaved memory systems (PDF)

Shyue-Kung Lu , Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan
Sy-Yen Kuo , Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan
pp. 354-359

A diagnostic network for massively parallel processing systems (PDF)

Yoon-Hwa Choi , Dept. of Comput. Eng., Hong Ik Univ., Seoul, South Korea
Yu-Seok Kim , Dept. of Comput. Eng., Hong Ik Univ., Seoul, South Korea
pp. 348-353

Experiments of faults on the "Happa" system and a proposal of backup RAM technique (PDF)

K. Iwasaki , Fac. of Eng., Chiba Univ., Japan
H. Yoshikawa , Fac. of Eng., Chiba Univ., Japan
A. Furuta , Fac. of Eng., Chiba Univ., Japan
pp. 343-347

A partial scan algorithm based on reduced scan shift (PDF)

Y. Higami , Dept. of Appl. Phys., Osaka Univ., Japan
S. Kajihara , Dept. of Appl. Phys., Osaka Univ., Japan
K. Kinoshita , Dept. of Appl. Phys., Osaka Univ., Japan
pp. 336-341

Test time reduction for scan-designed circuits by sliding compatibility (PDF)

Jau-Shien Chang , Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan
Chen-Shang Lin , Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan
pp. 330-335

Two techniques for minimizing power dissipation in scan circuits during test application (PDF)

S. Chakravarty , Dept. of Comput. Sci., State Univ. of New York, Buffalo, NY, USA
V.P. Dabholkar , Dept. of Comput. Sci., State Univ. of New York, Buffalo, NY, USA
pp. 324-329

Data path synthesis for easy testability (PDF)

M.K. Dhodhi , Dept. of Electr. & Comput. Eng., Kuwait Univ., Safat, Kuwait
I. Ahmad , Dept. of Electr. & Comput. Eng., Kuwait Univ., Safat, Kuwait
A.A. Ismaeel , Dept. of Electr. & Comput. Eng., Kuwait Univ., Safat, Kuwait
pp. 317-322

On full path delay fault testability of combinational circuits (PDF)

Xiaodong Xie , Dept. of Electr. Eng., Rochester Univ., NY, USA
A. Albicki , Dept. of Electr. Eng., Rochester Univ., NY, USA
pp. 311-316

Testable synthesis and testing of finite state machines (PDF)

Chen-Yeh Liu , Dept. of Comput. Sci., Chung-Hua Polytech. Inst., Hsinchu, Taiwan
pp. 305-310

Automatic program generator for simulation-based processor verification (PDF)

H. Iwashita , Fujitsu Labs. Ltd., Kawasaki, Japan
S. Kowatari , Fujitsu Labs. Ltd., Kawasaki, Japan
T. Nakata , Fujitsu Labs. Ltd., Kawasaki, Japan
F. Hirose , Fujitsu Labs. Ltd., Kawasaki, Japan
pp. 298-303

Automatic test generation for functional verification of microprocessors (PDF)

J. Miyake , Semicond. Res. Center, Matsushita Electr. Ind. Co. Ltd., Japan
G. Brown , Semicond. Res. Center, Matsushita Electr. Ind. Co. Ltd., Japan
M. Ueda , Semicond. Res. Center, Matsushita Electr. Ind. Co. Ltd., Japan
T. Nishiyama , Semicond. Res. Center, Matsushita Electr. Ind. Co. Ltd., Japan
pp. 292-297

Time-space modal model checking towards verification of bit-slice architecture (PDF)

H. Hiraishi , Dept. of Inf. & Commun. Sci., Kyoto Sangyo Univ., Japan
pp. 287-291

Minimum test sets for locally exhaustive testing of combinational circuits with five outputs (PDF)

T. Yokohira , Fac. of Eng., Okayama Univ., Japan
T. Shimizu , Fac. of Eng., Okayama Univ., Japan
H. Michinishi , Fac. of Eng., Okayama Univ., Japan
Y. Sugiyama , Fac. of Eng., Okayama Univ., Japan
T. Okamoto , Fac. of Eng., Okayama Univ., Japan
pp. 280-285

Design of pseudo-random patterns with low linear dependence and equi-distribution (PDF)

S. Matsufuji , Dept. of Inf. Sci., Saga Univ., Japan
S.-I. Tadaki , Dept. of Inf. Sci., Saga Univ., Japan
T. Yamanaka , Dept. of Inf. Sci., Saga Univ., Japan
pp. 274-279

A unified method for assembling global test schedules (PDF)

A. Stroele , Inst. of Comput. Design & Fault Tolerance, Karlsruhe Univ., Germany
pp. 268-273

Design verification by using universal test sets (PDF)

Beyin Chen , Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan
Chong Len Lee , Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan
pp. 261-266

Gate-level design diagnosis using a learning-based search strategy (PDF)

I. Pomeranz , Dept. of Electr. & Comput. Eng., Iowa Univ., Iowa City, IA, USA
S.M. Reddy , Dept. of Electr. & Comput. Eng., Iowa Univ., Iowa City, IA, USA
pp. 255-260

Boolean process-an analytical approach to circuit representation (PDF)

Yinghua Min , Inst. of Comput. Technol., Acad. Sinica, Beijing, China
pp. 249-254

Evaluations of various TPG circuits for use in two-pattern testing (PDF)

K. Furuya , Dept. of Inf. & Syst. Eng., Chuo Univ., Tokyo, Japan
S. Yamazaki , Dept. of Inf. & Syst. Eng., Chuo Univ., Tokyo, Japan
M. Sato , Dept. of Inf. & Syst. Eng., Chuo Univ., Tokyo, Japan
pp. 242-247

Design of random pattern testable floating point adders (PDF)

J. Rajski , Dept. of Electr. Eng., McGill Univ., Montreal, Que., Canada
J. Tyszer , Dept. of Electr. Eng., McGill Univ., Montreal, Que., Canada
pp. 227-232

Efficient test sequence generation for localization of multiple faults in communication protocols (PDF)

Y. Kakuda , Dept. of Inf. & Comput. Sci., Osaka Univ., Japan
H. Yukitomo , Dept. of Inf. & Comput. Sci., Osaka Univ., Japan
S. Kusumoto , Dept. of Inf. & Comput. Sci., Osaka Univ., Japan
T. Kikuno , Dept. of Inf. & Comput. Sci., Osaka Univ., Japan
pp. 214-219

Software design verification using FTA (PDF)

T. Fukuya , Res. & Dev. Center, Toshiba Corp., Kawasaki, Japan
M. Hirayama , Res. & Dev. Center, Toshiba Corp., Kawasaki, Japan
Y. Mihara , Res. & Dev. Center, Toshiba Corp., Kawasaki, Japan
pp. 208-213

Design in fault isolating of ternary cellular arrays using ternary decision diagrams (PDF)

N. Kamiura , Dept. of Comput. Eng., Himeji Inst. of Technol., Hyogo, Japan
H. Satoh , Dept. of Comput. Eng., Himeji Inst. of Technol., Hyogo, Japan
Y. Hata , Dept. of Comput. Eng., Himeji Inst. of Technol., Hyogo, Japan
K. Yamato , Dept. of Comput. Eng., Himeji Inst. of Technol., Hyogo, Japan
pp. 201-206

A new testable design of logic circuits under highly observable condition (PDF)

W. Xiaoqing , Min. Coll., Akita Univ., Japan
H. Tamamoto , Min. Coll., Akita Univ., Japan
pp. 195-200

Detectability of spurious signals with limited propagation in combinational circuits (PDF)

F. Moll , Dept. of Electron. Eng., Univ. Politecnica de Catalunya, Barcelona, Spain
pp. 176-181

Analysis and improvement of testability measure approximation algorithms (PDF)

J. Bitner , Comput. Eng. Res. Center, Texas Univ., Austin, TX, USA
pp. 189-194

On crosstalk fault detection in hierarchical VLSI logic circuits (PDF)

A. Liaud , Inst. Nat. des Sci. Appliquees, Toulouse, France
J.Y. Fourniols , Inst. Nat. des Sci. Appliquees, Toulouse, France
E. Sicard , Inst. Nat. des Sci. Appliquees, Toulouse, France
pp. 182-187

A unified model for inter-gate and intra-gate CMOS bridging fault: the configuration ratio (PDF)

M. Renovell , Lab. d'Inf., Robotique et Microelectron., Univ. des Sci. et Tech. du Languedoc, Montpellier, France
P. Huc , Lab. d'Inf., Robotique et Microelectron., Univ. des Sci. et Tech. du Languedoc, Montpellier, France
Y. Bertrand , Lab. d'Inf., Robotique et Microelectron., Univ. des Sci. et Tech. du Languedoc, Montpellier, France
pp. 170-175

Easily testable realizations for generalized Reed-Muller expressions (PDF)

T. Sasao , Dept. of Comput. Sci. & Electron., Kyushu Inst. of Technol., Iizuka, Japan
pp. 157-162

Testability considerations in technology mapping (PDF)

I. Pomeranz , Dept. of Electr. & Comput. Eng., Iowa Univ., Iowa City, IA, USA
S.M. Reddy , Dept. of Electr. & Comput. Eng., Iowa Univ., Iowa City, IA, USA
pp. 151-156

The effect of fault detection by IDDq measurement for CMOS VLSIs (PDF)

J. Hirase , Microcomput. Div., Matsushita Electron. Corp., Japan
M. Hamada , Microcomput. Div., Matsushita Electron. Corp., Japan
pp. 144-149

A built-in I/sub DDQ/ test circuit utilizing upper and lower limits (PDF)

Y. Miura , Dept. of Electron. & Inf. Eng., Tokyo Metropolitan Univ., Japan
S. Naito , Dept. of Electron. & Inf. Eng., Tokyo Metropolitan Univ., Japan
pp. 138-143

Random test input generation for supply current testing of TTL combinational circuits (PDF)

M. Hashizume , Fac. of Eng., Tokushima Univ., Japan
I. Tsukimoto , Fac. of Eng., Tokushima Univ., Japan
T. Tamesada , Fac. of Eng., Tokushima Univ., Japan
pp. 132-137

Testing of analog integrated circuits based on power-supply current monitoring and discrimination analysis (PDF)

Z. Wang , Dept. of Electr. Eng., Katholieke Univ., Leuven, Belgium
G. Gielen , Dept. of Electr. Eng., Katholieke Univ., Leuven, Belgium
W. Sansen , Dept. of Electr. Eng., Katholieke Univ., Leuven, Belgium
pp. 126-131

Sequential test generation in massive observability environments (PDF)

P. Varma , CrossCheck Technol. Inc., San Jose, CA, USA
pp. 119-124

Efficient fault ordering for automatic test pattern generation for sequential circuits (PDF)

P.A. Krauss , Dept. of Electr. Eng., Tech. Univ. Munchen, Germany
M. Henftling , Dept. of Electr. Eng., Tech. Univ. Munchen, Germany
pp. 113-118

Test generation for redundant faults in combinational circuits by using delay effects (PDF)

X. Yu , Dept. of Comput. Sci., Ehime Univ., Matsuyama, Japan
H. Takahashi , Dept. of Comput. Sci., Ehime Univ., Matsuyama, Japan
Y. Takamatsu , Dept. of Comput. Sci., Ehime Univ., Matsuyama, Japan
pp. 107-112

A genetic approach to test generation for logic circuits (PDF)

T. Hayashi , Fac. of Eng., Mie Univ., Tsu, Japan
H. Kita , Fac. of Eng., Mie Univ., Tsu, Japan
pp. 101-106

Efficient diagnostic fault simulation for sequential circuits (PDF)

Jer Min Jou , Dept. of Electr. Eng., Nat. Cheng Kung Univ., Tainan, Taiwan
Shung-Chih Chen , Dept. of Electr. Eng., Nat. Cheng Kung Univ., Tainan, Taiwan
pp. 94-99

An approach of diagnosing single bridging faults in CMOS combinational circuits (PDF)

K. Yamazaki , Dept. of Comput. Sci., Meiji Univ., Kawasaki, Japan
T. Yamada , Dept. of Comput. Sci., Meiji Univ., Kawasaki, Japan
pp. 88-93

Efficiency improvements for multiple fault diagnosis of combinational circuits (PDF)

N. Yanagida , Dept. of Comput. Sci., Ehime Univ., Matsuyama, Japan
H. Takahashi , Dept. of Comput. Sci., Ehime Univ., Matsuyama, Japan
Y. Takamatsu , Dept. of Comput. Sci., Ehime Univ., Matsuyama, Japan
pp. 82-87

On the performance analysis of parallel processing for test generation (PDF)

T. Inoue , Graduate Sch. of Inf. Sci., Nara Inst. of Sci. & Technol., Japan
T. Fujii , Graduate Sch. of Inf. Sci., Nara Inst. of Sci. & Technol., Japan
H. Fujiwara , Graduate Sch. of Inf. Sci., Nara Inst. of Sci. & Technol., Japan
pp. 69-74

Test scheduling using test subsession partitioning (PDF)

Dong Xiang , Inst. of Comput. Technol., Acad. Sinica, Beijing, China
pp. 63-68

A sequential redundant fault identification scheme and its application to test generation (PDF)

Hsing-Chung Liang , Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan
Chung Len Lee , Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan
pp. 57-62

Efficient techniques for multiple fault test generation (PDF)

S. Kajihara , Dept. of Appl. Phys., Osaka Univ., Japan
R. Nishigaya , Dept. of Appl. Phys., Osaka Univ., Japan
T. Sumioka , Dept. of Appl. Phys., Osaka Univ., Japan
K. Kinoshita , Dept. of Appl. Phys., Osaka Univ., Japan
pp. 52-56

Strongly fail-safe interfaces based on concurrent checking (PDF)

M. Nicolaidis , Reliable Integrated Syst. Group, Inst. Nat. Polytech. de Grenoble, France
pp. 45-50

Application of byte error detecting codes to the design of self-checking circuits (PDF)

S. Pagey , Dept. of Electr. & Comput. Eng., Concordia Univ., Montreal, Que., Canada
A.J. Al-Khalili , Dept. of Electr. & Comput. Eng., Concordia Univ., Montreal, Que., Canada
pp. 39-44

Fault coverage analysis in monitored sequential circuits (PDF)

R.A. Parekhji , Dept. of Comput. Sci. & Eng., Inst. of Technol., Bombay, India
G. Venkatesh , Dept. of Comput. Sci. & Eng., Inst. of Technol., Bombay, India
S.D. Sherlekar , Dept. of Comput. Sci. & Eng., Inst. of Technol., Bombay, India
pp. 33-38

Bounding error masking in linear output space compression schemes (PDF)

S. Tarnick , Fault-Tolerant Comput. Group, Potsdam Univ., Germany
pp. 27-32

Delay fault propagation in synchronous sequential circuits (PDF)

P. Cavallera , Lab. d'Inf. de Robotique et de Microelectron., Univ. des Sci. et Tech. du Languedoc, Montpellier, France
P. Girard , Lab. d'Inf. de Robotique et de Microelectron., Univ. des Sci. et Tech. du Languedoc, Montpellier, France
C. Landrault , Lab. d'Inf. de Robotique et de Microelectron., Univ. des Sci. et Tech. du Languedoc, Montpellier, France
S. Pravossoudovitch , Lab. d'Inf. de Robotique et de Microelectron., Univ. des Sci. et Tech. du Languedoc, Montpellier, France
pp. 20-25

Fault detection by transient transition count testing (PDF)

Kuo Chan Huang , Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan
Ming Yu Chen , Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan
Chung Len Lee , Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan
pp. 14-19

Hardware-accelerated parallel-pattern/multiple-fault-propagation concurrent fault simulation (PDF)

W. Hahn , Fac. of Math. & Comput. Sci., Passau Univ., Germany
A. Hagerer , Fac. of Math. & Comput. Sci., Passau Univ., Germany
pp. 8-13
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