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Proceedings First Asian Test Symposium (1992)
Hiroshima, Japan
Nov. 26, 1992 to Nov. 27, 1992
ISBN: 0-8186-2985-1
TABLE OF CONTENTS

Reducing BIST hardware by test schedule optimization (PDF)

A.P. Stroele , Inst. of Comput. Design & Fault Tolerance, Karlsruhe Univ., Germany
pp. 253-258

A fuzzy multiple signature compaction scheme for BIST (PDF)

Yuejian Wu , Dept. of Electr. Eng., British Columbia Univ., Vancouver, BC, Canada
A. Ivanov , Dept. of Electr. Eng., British Columbia Univ., Vancouver, BC, Canada
pp. 247-252

Accumulator-based compaction for built-in self test of data-path architectures (PDF)

M. Kassab , Dept. of Electr. Eng., McGill Univ., Montreal, Que., Canada
J. Rajski , Dept. of Electr. Eng., McGill Univ., Montreal, Que., Canada
J. Tyszer , Dept. of Electr. Eng., McGill Univ., Montreal, Que., Canada
pp. 241-246

Synthesis of autonomous TPG circuits oriented for two-pattern testing (PDF)

K. Furuya , Dept. of Inf. & Syst. Eng., Chuo Univ., Tokyo, Japan
S. Seki , Dept. of Inf. & Syst. Eng., Chuo Univ., Tokyo, Japan
pp. 235-240

Exhaustive two-pattern generation with cellular automata (PDF)

S. Nandi , Indian Inst. of Technol., Kharagpur, India
pp. 230-234

Design for testability in a 200 MFLOPS vector-pipelined processor (VPP)-ULSI (PDF)

Y. Hagihara , NEC Corp., Tokyo, Japan
C. Ohkubo , NEC Corp., Tokyo, Japan
F. Okamoto , NEC Corp., Tokyo, Japan
H. Yamada , NEC Corp., Tokyo, Japan
M. Takada , NEC Corp., Tokyo, Japan
T. Enomoto , NEC Corp., Tokyo, Japan
pp. 223-228

Syndrome testable design software package, instrument and Syndrome testing system for sequential circuits (PDF)

Fanglei Wang , Shanghai Univ. of Sci. & Technol., China
Jijie Wang , Shanghai Univ. of Sci. & Technol., China
pp. 218-222

A test application scheme for embedded full-scan circuits to reduce testing costs (PDF)

I. Pomeranz , Dept. of Electr. & Comput. Eng., Iowa Univ., Iowa City, IA, USA
S.M. Reddy , Dept. of Electr. & Comput. Eng., Iowa Univ., Iowa City, IA, USA
pp. 206-211

Synthesis of easily testable sequential circuits with checking sequences (PDF)

S. Shibatani , Dept. of Appl. Phys., Osaka Univ., Japan
K. Kinoshita , Dept. of Appl. Phys., Osaka Univ., Japan
pp. 200-205

Synthesis for testability of PLA based finite state machines (PDF)

M.J. Avedillo , Dept. de Diseno Analogico, CNM, Sevilla, Spain
J.M. Quintana , Dept. de Diseno Analogico, CNM, Sevilla, Spain
J.L. Huertas , Dept. de Diseno Analogico, CNM, Sevilla, Spain
pp. 194-199

Three-valued computer system diagnosis implemented by artificial neural network (PDF)

Tinghuai Chen , Comput. Inst., Chongqing Univ., Sichuan, China
Kaigui Wu , Comput. Inst., Chongqing Univ., Sichuan, China
Yundi Wu , Comput. Inst., Chongqing Univ., Sichuan, China
pp. 187-191

A practical approach for the diagnosis of a MIMD network (PDF)

C. Aktouf , IMAG/LGI, Grenoble, France
G. Mazare , IMAG/LGI, Grenoble, France
C. Robach , IMAG/LGI, Grenoble, France
R. Velazco , IMAG/LGI, Grenoble, France
pp. 182-186

Break fault model and fault collapsing analysis for PLA's (PDF)

Gwo-Haur Hwang , Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsin-Chu, Taiwan
Wen-Zen Shen , Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsin-Chu, Taiwan
pp. 176-181

A method of diagnosing logical faults in combinational circuits (PDF)

K. Yamazaki , Dept. of Comput. Sci., Meiji Univ., Kawasaki, Japan
T. Yamada , Dept. of Comput. Sci., Meiji Univ., Kawasaki, Japan
pp. 170-175

Novel image-based LSI diagnostic method using E-beam without CAD database (PDF)

T. Nakamura , Schlumberger KK, Kanagawa, Japan
Y. Hanagama , Schlumberger KK, Kanagawa, Japan
K. Nikawa , Schlumberger KK, Kanagawa, Japan
T. Tsujide , Schlumberger KK, Kanagawa, Japan
K. Morohashi , Schlumberger KK, Kanagawa, Japan
pp. 164-169

Laser injection of spot defects on integrated circuits (PDF)

R. Velazco , LGI, Grenoble, France
B. Martinet , LGI, Grenoble, France
pp. 158-163

A control constrained test scheduling approach for VLSI circuits (PDF)

S. Misra , Motorola India Electronics Ltd., Bangalore, India
pp. 145-150

A concurrent fault detection method for superscalar processors (PDF)

A.P. Pawlovsky , Hitachi Central Res. Lab., Hitachi Ltd., Koigakubo, Japan
M. Hanawa , Hitachi Central Res. Lab., Hitachi Ltd., Koigakubo, Japan
pp. 139-144

Techniques for reducing hardware requirement of self checking combinational circuits (PDF)

S. Pagey , Dept. of Comput. Sci. & Eng., Indian Inst. of Technol., Bombay, India
S.D. Sherlekar , Dept. of Comput. Sci. & Eng., Indian Inst. of Technol., Bombay, India
G. Venkatesh , Dept. of Comput. Sci. & Eng., Indian Inst. of Technol., Bombay, India
pp. 132-138

Behavioral design and test assistance for pipelined processors (PDF)

H. Iwashita , Fujitsu Lab. Ltd., Kawasaki, Japan
T. Nakata , Fujitsu Lab. Ltd., Kawasaki, Japan
F. Hirose , Fujitsu Lab. Ltd., Kawasaki, Japan
pp. 8-13

Minimum verification test set for combinational circuit (PDF)

H. Michinishi , Fac. of Eng., Okayama Univ., Japan
T. Yokohira , Fac. of Eng., Okayama Univ., Japan
T. Okamoto , Fac. of Eng., Okayama Univ., Japan
pp. 14-19

Test set compaction for combinational circuits (PDF)

Jau-Shien Chang , Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan
Chen-Shang Lin , Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan
pp. 20-25

Fault simulation based on value difference (PDF)

Ching Pin Wu , Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsin-Chu, Taiwan
Chung Len Lee , Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsin-Chu, Taiwan
Wen Zen Shen , Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsin-Chu, Taiwan
pp. 28-33

Accelerated fault simulation utilizing multiple-fault propagation (PDF)

Y. Xing , Mesa Res. Inst., Twente Univ., Enschede, Netherlands
G. van Brakel , Mesa Res. Inst., Twente Univ., Enschede, Netherlands
H.G. Kerkhoff , Mesa Res. Inst., Twente Univ., Enschede, Netherlands
pp. 34-39

Reduction of dynamic memory usage in concurrent fault simulation for synchronous sequential circuits (PDF)

K. Kim , Dept. of Electr. & Comput. Eng., Wisconsin Univ., Madison, WI, USA
K.K. Saluja , Dept. of Electr. & Comput. Eng., Wisconsin Univ., Madison, WI, USA
pp. 40-45

Highly efficient fault simulation exploiting hierarchy in circuit description (PDF)

B.H. Seiss , Tech. Univ. of Munich, Germany
H.C. Wittmann , Tech. Univ. of Munich, Germany
pp. 46-51

Test input vectors for supply current testing of TTL combinational circuits (PDF)

M. Hashizume , Fac. of Eng., Tokushima Univ., Japan
T. Tamesada , Fac. of Eng., Tokushima Univ., Japan
I. Tsukimoto , Fac. of Eng., Tokushima Univ., Japan
pp. 58-63

Quiescent current testing of combinational circuits with bridging faults (PDF)

M. Roca , Dept. of Phys., Univ. Illes Balears, Palma de Mallorca, Spain
pp. 64-69

A current testing for CMOS logic circuits applying random patterns and monitoring dynamic power supply current (PDF)

H. Tamamoto , Dept. of Inf. Eng., Akita Univ., Japan
H. Yokoyama , Dept. of Inf. Eng., Akita Univ., Japan
Y. Narita , Dept. of Inf. Eng., Akita Univ., Japan
pp. 70-75

A complement-based fast algorithm to generate universal test sets for combinational function blocks (PDF)

Beyin Chen , Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsin-Chu, Taiwan
Chung Len Lee , Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsin-Chu, Taiwan
pp. 76-81

Practical considerations in ATPG using CrossCheck technology (PDF)

S. Chandra , CrossCheck Technol. Inc., San Jose, CA, USA
N. Jacobson , CrossCheck Technol. Inc., San Jose, CA, USA
G. Srinath , CrossCheck Technol. Inc., San Jose, CA, USA
pp. 88-93

Functional tests for arbitration SRAM-type FIFOs (PDF)

A.J. van de Goor , Dept. of Electr. Eng., Delft Univ. of Technol., Netherlands
pp. 96-101

Issues in fault modelling and testing of micropipelines (PDF)

S. Pagey , Dept. of Comput. Sci. & Eng., Indian Inst. of Technol., Bombay, India
S.D. Sherlekar , Dept. of Comput. Sci. & Eng., Indian Inst. of Technol., Bombay, India
G. Venkatesh , Dept. of Comput. Sci. & Eng., Indian Inst. of Technol., Bombay, India
pp. 107-111

Automatic behavioral test pattern generation for digital circuits (PDF)

A.-L. Courbis , L.E.R.I., Nimes, France
J.-F. Santucci , L.E.R.I., Nimes, France
N. Giambiasi , L.E.R.I., Nimes, France
pp. 112-117

Methods to measure and to enhance the testability of behavioral descriptions of digital circuits (PDF)

J.-F. Santucci , L.E.R.I., Nimes, France
G. Dray , L.E.R.I., Nimes, France
M. Boumedine , L.E.R.I., Nimes, France
N. Giambiasi , L.E.R.I., Nimes, France
pp. 118-123

Cyclogen: automatic, functional-level test generator (PDF)

B. Ayari , Dept. of Electr. & Comput. Eng., Ecole Polytech. de Montreal, Que., Canada
B. Kaminska , Dept. of Electr. & Comput. Eng., Ecole Polytech. de Montreal, Que., Canada
pp. 124-129
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