CSDL - Second Working Conference on Asynchronous Design Methodologies - Table of Contents

Proceedings Second Working Conference on Asynchronous Design Methodologies (1995)

London, England

May 30, 1995 to May 31, 1995

ISBN: 0-8186-7098-3

TABLE OF CONTENTS

Proceedings Second Working Conference on Asynchronous Design Methodologies (PDF)

pp. i

Message from the Chair (PDF)

pp. vii

Program Committee (PDF)

pp. viii

Session 1

Tutorial (PDF)

pp. null

Session 2: Pipelines, Session Chair: Jo Ebergen, Waterloo University

Performance evaluation of asynchronous logic pipelines with data dependent processing delays (Abstract)

D. Kearney , Sch. of Electr. Eng, Univ. of South Australia, Adelaide, SA, Australia

N.W. Bergmann , Sch. of Electr. Eng, Univ. of South Australia, Adelaide, SA, Australia

pp. 4

New CMOS VLSI linear self-timed architectures (Abstract)

A.J. Acosta , Dept. de Diseno de Circuitos Analogicos, Seville Univ., Spain

M. Bellido , Dept. de Diseno de Circuitos Analogicos, Seville Univ., Spain

M. Valencia , Dept. de Diseno de Circuitos Analogicos, Seville Univ., Spain

A. Barriga , Dept. de Diseno de Circuitos Analogicos, Seville Univ., Spain

R. Jimenez , Dept. de Diseno de Circuitos Analogicos, Seville Univ., Spain

J.L. Huertas , Dept. de Diseno de Circuitos Analogicos, Seville Univ., Spain

pp. 14

Low-latency asynchronous FIFO buffers (Abstract)

J.T. Yantchev , Dept. of Comput. Sci., Adelaide Univ., SA, Australia

C.G. Huang , Dept. of Comput. Sci., Adelaide Univ., SA, Australia

M.B. Josephs , Dept. of Comput. Sci., Adelaide Univ., SA, Australia

I.M. Nedelchev , Dept. of Comput. Sci., Adelaide Univ., SA, Australia

pp. 24

Designing an asynchronous pipeline token ring interface (Abstract)

A. Yakovlev , Dept. of Comput. Sci., Newcastle upon Tyne Univ., UK

V. Varshavsky , Dept. of Comput. Sci., Newcastle upon Tyne Univ., UK

V. Marakhovsky , Dept. of Comput. Sci., Newcastle upon Tyne Univ., UK

A. Semenov , Dept. of Comput. Sci., Newcastle upon Tyne Univ., UK

pp. 32

Session 3: Silicon Compilation I, Session Chair, Sylvia Jennings, South Bank University

VLSI programming of a low-power asynchronous Reed-Solomon decoder for the DCC player (Abstract)

J. Kessels , Philips Res. Lab., Eindhoven, Netherlands

pp. 44

Single-rail handshake circuits (Abstract)

A. Peeters , Dept. of Math. & Comput. Sci., Eindhoven Univ. of Technol., Netherlands

K. van Berkel , Dept. of Math. & Comput. Sci., Eindhoven Univ. of Technol., Netherlands

pp. 53

High-level test evaluation of asynchronous circuits (Abstract)

R. van de Wiel , Dept. of Math. & Comput. Sci., Eindhoven Univ. of Technol., Netherlands

pp. 63

A single-rail re-implementation of a DCC error detector using a generic standard-cell library (Abstract)

K. Van Berkel , Philips Res. Lab., Eindhoven, Netherlands

R. Burgess , Philips Res. Lab., Eindhoven, Netherlands

J. Kessels , Philips Res. Lab., Eindhoven, Netherlands

A. Peeters , Philips Res. Lab., Eindhoven, Netherlands

M. Roncken , Philips Res. Lab., Eindhoven, Netherlands

F. Schalij , Philips Res. Lab., Eindhoven, Netherlands

R. van de Wiel , Philips Res. Lab., Eindhoven, Netherlands

pp. 72

Session 4: Silicon Compilation II, Session Chair: John Brzozowshi, Waterloo University

Sequencer circuits for VLSI programming (Abstract)

A. Bailey , Dept. of Math. & Comput. Sci., Eindhoven Univ. of Technol., Netherlands

M.B. Josephs , Dept. of Math. & Comput. Sci., Eindhoven Univ. of Technol., Netherlands

pp. 82

A hybrid asynchronous system design environment (Abstract)

C. Farnsworth , Dept. of Comput. Sci., Manchester Univ., UK

D.A. Edwards , Dept. of Comput. Sci., Manchester Univ., UK

Jianwei Liu , Dept. of Comput. Sci., Manchester Univ., UK

S.S. Sikand , Dept. of Comput. Sci., Manchester Univ., UK

pp. 91

Stretching quasi delay insensitivity by means of extended isochronic forks (Abstract)

K. Van Berkel , Philips Res. Lab., Eindhoven, Netherlands

F. Huberts , Philips Res. Lab., Eindhoven, Netherlands

A. Peeters , Philips Res. Lab., Eindhoven, Netherlands

pp. 99

Session 5: Synthesis/Verification, Session Chair: Dave Protheroe, South Bank University

Relative liveness: from intuition to automated verification (Abstract)

R. Negulescu , Dept. of Comput. Sci., Waterloo Univ., Ont., Canada

J.A. Brzozowski , Dept. of Comput. Sci., Waterloo Univ., Ont., Canada

pp. 108

Optimised state assignment for asynchronous circuit synthesis (Abstract)

C. Ykman-Couvreur , IMEC, Leuven, Belgium

B. Lin , IMEC, Leuven, Belgium

pp. 118

Hierarchical gate-level verification of speed-independent circuits (Abstract)

O. Roig , Dept. of Comput. Archit., Univ. Politecnica de Catalunya, Barcelona, Spain

J. Cortadella , Dept. of Comput. Archit., Univ. Politecnica de Catalunya, Barcelona, Spain

E. Pastor , Dept. of Comput. Archit., Univ. Politecnica de Catalunya, Barcelona, Spain

pp. 128

Technology mapping of timed circuits (Abstract)

C.J. Myers , Comput. Syst. Lab., Stanford Univ., CA, USA

P.A. Beerel , Comput. Syst. Lab., Stanford Univ., CA, USA

T.H.-Y. Meng , Comput. Syst. Lab., Stanford Univ., CA, USA

pp. 138

Session 6: Testing; Completion-Detection, Session Chair: Kees van Berkel, Phillips Research Laboratories

Testing C-elements is not elementary (Abstract)

J.A. Brzozowski , Dept. of Comput. Sci., Waterloo Univ., Ont., Canada

K. Raahemifar , Dept. of Comput. Sci., Waterloo Univ., Ont., Canada

pp. 150

Testing self-timed circuits using partial scan (Abstract)

A. Khoche , Dept. of Comput. Sci., Utah Univ., Salt Lake City, UT, USA

E. Brunvand , Dept. of Comput. Sci., Utah Univ., Salt Lake City, UT, USA

pp. 160

Asynchronous circuits based on multiple localised current-sensing completion detection (Abstract)

E. Grass , Dept. of Electron. & Electr. Eng., Loughborough Univ. of Technol., UK

S. Jones , Dept. of Electron. & Electr. Eng., Loughborough Univ. of Technol., UK

pp. 170

Session 7: Microprocessors, Session Chair: Doug Edwards, Manchester University

ECSTAC: a fast asynchronous microprocessor (Abstract)

S.V. Morton , Southbank Univ., London, UK

S.S. Appleton , Southbank Univ., London, UK

M.J. Liebelt , Southbank Univ., London, UK

pp. 180

Micronets: a model for decentralising control in asynchronous processor architectures (Abstract)

D.K. Arvind , Dept. of Comput. Sci., Edinburgh Univ., UK

R.D. Mullins , Dept. of Comput. Sci., Edinburgh Univ., UK

V.E.F. Rebello , Dept. of Comput. Sci., Edinburgh Univ., UK

pp. 190

Hades-towards the design of an asynchronous superscalar processor (Abstract)

C.J. Elston , Div. of Comput. Sci., Hertfordshire Univ., Hatfield, UK

D.B. Christianson , Div. of Comput. Sci., Hertfordshire Univ., Hatfield, UK

P.A. Findlay , Div. of Comput. Sci., Hertfordshire Univ., Hatfield, UK

G.B. Steven , Div. of Comput. Sci., Hertfordshire Univ., Hatfield, UK

pp. 200

ARAS: asynchronous RISC architecture simulator (Abstract)

Chia-Hsing Chien , Comput. & Commun. Res. Center, Washington Univ., St. Louis, MO, USA

M.A. Franklin , Comput. & Commun. Res. Center, Washington Univ., St. Louis, MO, USA

Tienyo Pan , Comput. & Commun. Res. Center, Washington Univ., St. Louis, MO, USA

P. Prabhu , Comput. & Commun. Res. Center, Washington Univ., St. Louis, MO, USA

pp. 210

Session 8

Status Report on AMULET (PDF)

pp. null

Author Index (PDF)

pp. 223