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Proceedings of 1994 IEEE Symposium on Advanced Research in Asynchronous Circuits and Systems (1994)
Salt Lake City, UT, USA
Nov. 3, 1994 to Nov. 5, 1994
ISBN: 0-8186-6210-7

Bounded delay timing analysis of a class of CSP programs with choice (PDF)

H. Hulgaard , Dept. of Comput. Sci. & Eng., Washington Univ., Seattle, WA, USA
pp. 2-11

Timing-reliability evaluation of asynchronous circuits based on different delay models (PDF)

M. Kuwako , Dept. of Comput. Sci., Tokyo Inst. of Technol., Japan
pp. 22-31

Characterizing speed-independence of high-level designs (PDF)

M. Kishinevsky , Dept. of Comput. Sci., Tech. Univ. Denmark, Lyngby, Denmark
pp. 44-53

Retargeting a hardware compiler proof using protocol converters (PDF)

G. Brown , Dept. of Electr. Eng., Cornell Univ., Ithaca, NY, USA
pp. 54-63

Verification of the speed-independent circuits by STG unfoldings (PDF)

A. Kondratyev , Dept. of Comput. Hardware, Aizu Univ., Fukushima, Japan
pp. 64-75

How fast will the flip flop? (PDF)

M.R. Greenstreet , Dept. of Comput. Sci., British Columbia Univ., Vancouver, BC, Canada
pp. 77-86

Pipeline synchronization (PDF)

J.N. Seizovic , Myricom Inc., Arcadia, CA, USA
pp. 87-96

Metastable-robust self-timed circuit synthesis from live safe simple signal transition graphs (Abstract)

E.C.Y. Chung , Dept. of Electr. & Comput. Syst. Eng., Monash Univ., Clayton, Vic., Australia
pp. 97-105

Designing asynchronous circuits from behavioural specifications with internal conflicts (PDF)

J. Cortadella , Dept. of Comput. Archit., Univ. Politecnica de Catalunya, Barcelona, Spain
pp. 106-115

Performance comparison of asynchronous adders (PDF)

M.A. Franklin , Comput. & Commun. Res. Center, Washington Univ., St. Louis, MO, USA
pp. 117-125

An asynchronous pipelined lattice structure filter (PDF)

U.V. Cummings , Dept. of Comput. Sci., California Inst. of Technol., Pasadena, CA, USA
pp. 126-133

An event controlled reconfigurable multi-chip FFT (PDF)

S.V. Morton , Dept. of Electr. & Electron. Eng., Adelaide Univ., SA, Australia
pp. 144-153

A technique for estimating power in asynchronous circuits (PDF)

P. Kudva , Dept. of Comput. Sci., Utah Univ., Salt Lake City, UT, USA
pp. 166-175

Low-energy asynchronous memory design (PDF)

J.A. Tierno , California Inst. of Technol., Pasadena, CA, USA
pp. 176-185

Efficient building blocks for delay insensitive circuits (PDF)

P. Patra , Dept. of Comput. Sci., Texas Univ., Austin, TX, USA
pp. 196-205

Composable specifications for asynchronous systems using UNITY (PDF)

M. Bickford , Odyssey Res. Associates Inc., Ithaca, NY, USA
pp. 216-227

Delay-insensitive solutions to the committee problem (PDF)

I. Benko , Dept. of Comput. Sci., Waterloo Univ., Ont., Canada
pp. 228-237

Testing micropipelines (PDF)

A. Khoche , Dept. of Comput. Sci., Utah Univ., Salt Lake City, UT, USA
pp. 239-246

Author index (PDF)

pp. 258
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