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Proceedings of 1998 Asia and South Pacific Design Automation Conference (1998)
Yokohama, Japan
Feb. 13, 1998 to Feb. 13, 1998
ISBN: 0-7803-4425-1
TABLE OF CONTENTS

HW-SW co-synthesis: the present and the future (PDF)

S. Parameswaran , Dept. of Comput. Sci. & Electr. Eng., Queensland Univ., Australia
pp. 19-22

A heuristic algorithm to design AND-OR-EXOR three-level networks (PDF)

D. Debnath , Dept. of Comput. Sci. & Electron., Kyushu Inst. of Technol., Iizuka, Japan
pp. 69-74

ETDD-based synthesis of term-based FPGAs for incompletely specified Boolean functions (PDF)

Gueesang Lee , Dept. of Comput. Sci., Chonnam Nat. Univ., Kwangju, South Korea
pp. 75-80

Optimized array index computation in DSP programs (PDF)

R. Leupers , Dept. of Comput. Sci., Dortmund Univ., Germany
pp. 87-92

Binding and scheduling algorithms for highly retargetable compilation (PDF)

M. Yamaguchi , Precision Technol. Center, Sharp Corp., Nara, Japan
pp. 93-98

Unrolling loops with indeterminate loop counts in system level pipelines (PDF)

Hui Guo , Dept. of Comput. Sci. & Electr. Eng., Queensland Univ., Brisbane, Qld., Australia
pp. 99-104

Quantitative selection of media benchmarks (PDF)

Chunho Lee , Dept. of Comput. Sci., California Univ., Los Angeles, CA, USA
pp. 105-110

Inverse modeling-a promising approach to know what is made and what should be made (PDF)

S. Yamaguchi , Technol. Dev. Div., Fujitsu Labs. Ltd., Kawasaki, Japan
pp. 117-121

TCAD/DA for MPU and ASIC development (PDF)

H. Masuda , Device Dev. Center, Hitachi Ltd., Tokyo, Japan
pp. 129-134

Coupling Of Synthesis And Layout: Challenges And Solutions (PDF)

J. Cong , University of California at Los Angels
pp. 135-136

Logical-physical co-design for deep submicron circuits: challenges and solutions (PDF)

M. Pedram , Dept. of Electr. Eng. Syst., Univ. of Southern California, Los Angeles, CA, USA
pp. 137-142

An efficient variable-length tap FIR filter chip (PDF)

Sung Hyun Yoon , Sch. of Electr. & Electron. Eng., Ajou Univ., Suwon, South Korea
pp. 157-161

Effective simulation for the giga-scale massively parallel supercomputer SR2201 (PDF)

K. Suzuki , Software Technol. Dev. Center, Hitachi Ltd., Kanagawa, Japan
pp. 163-168

A hardware software cosimulation backplane with automatic interface generation (PDF)

Wonyong Sung , Dept. of Comput. Eng., Seoul Nat. Univ., South Korea
pp. 177-182

On the CSC property of signal transition graph specifications for asynchronous circuit design (PDF)

M. Sahni , Dept. of Comput. Sci., Tokyo Inst. of Technol., Japan
pp. 183-189

Practical synthesis of speed-independent circuits using unfoldings (PDF)

Uisok Kim , Dept. of Inf. & Commun., K-JIST, Kwangju, South Korea
pp. 191-196

Automated design of wave pipelined multiport register files (PDF)

K. Takano , Graduate Sch. of Inf. Sci., Tohoku Univ., Sendai, Japan
pp. 197-202

Design And EDA Roadmap (PDF)

G. Ledenbach , SEMATECH
pp. 203

Considering testability during high-level design (PDF)

S. Dey , Dept. of Electr. & Comput. Eng., California Univ., San Diego, La Jolla, CA, USA
pp. 205-210

Partial scan design methods based on internally balanced structure (PDF)

T. Takasaki , Graduate Sch. of Inf. Sci., Nara Inst. of Sci. & Technol., Japan
pp. 211-216

Model checking: its basics and reality (PDF)

M. Fujita , Fujitsu Lab. of America, Santa Clara, CA, USA
pp. 217-222

ALPS: an automatic layouter for pass-transistor cell synthesis (PDF)

Y. Sasaki , Central Res. Lab., Hitachi Ltd., Tokyo, Japan
pp. 227-232

Software licensing models in the EDA industry (PDF)

D.R. Bettadapur , Intel Corp., Santa Clara, CA, USA
pp. 235-239

Pre-layout delay calculation specification for CMOS ASIC libraries (PDF)

H. Edamatsu , Corp. Semicond. Dev. Div., Matsushita Electr. Ind. Co. Ltd., Moriguchi, Japan
pp. 241-248

CHDStd-a model for deep submicron design tools (PDF)

D. Cottrell , Silicon Integration Initiative, Austin, TX, USA
pp. 249-255

Module selection using manufacturing information (PDF)

H. Tomiyama , Dept. of Comput. Sci. & Commun. Eng., Kyushu Univ., Fukuoka, Japan
pp. 275-281

Techniques for functional test pattern execution (PDF)

I. Hong , Dept. of Comput. Sci., California Univ., Los Angeles, CA, USA
pp. 283-288

Heterogeneous BISR-approach using system level synthesis flexibility (PDF)

I. Hong , Dept. of Comput. Sci., California Univ., Los Angeles, CA, USA
pp. 289-294

An integrated flow for technology remapping and placement of sub-half-micron circuits (PDF)

J. Lou , Dept. of Electr. Eng. Syst., Univ. of Southern California, Los Angeles, CA, USA
pp. 295-300

Scan-chain optimization algorithms for multiple scan-paths (PDF)

S. Kobayashi , C&C Media Res. Labs., NEC Corp., Kawasaki, Japan
pp. 301-306

A clock-gating method for low-power LSI design (PDF)

T. Kitahara , Semicond. DA & Test Eng. Center, Toshiba Corp., Kawasaki, Japan
pp. 307-312

Power reduction in microprocessor chips by gated clock routing (PDF)

Jaewon Oh , Dept. of Electr. Eng. Syst., Univ. of Southern California, Los Angeles, CA, USA
pp. 313-318

TITAC-2: an asynchronous 32-bit microprocessor (PDF)

A. Takamura , Graduate Sch. of Inf. Sci. & Eng., Tokyo Inst. of Technol., Japan
pp. 319-320

Power-Pro: programmable power management architecture (PDF)

T. Ishihara , Dept. of Comput. Sci. & Commun. Eng., Kyushu Univ., Fukuoka, Japan
pp. 321-322

A design of sound synthesis IC (PDF)

Ho Keun Jang , Dept. of Electron., Pusan Nat. Univ., South Korea
pp. 327-328

An efficient 2-D convolver chip for real-time image processing (PDF)

Se Young Eun , Sch. of Electr. & Electron. Eng., Ajou Univ., Suwon, South Korea
pp. 329-330

FPGA for high-performance bit-serial pipeline datapath (PDF)

T. Isshiki , Dept. of Electr. & Electron. Eng., Tokyo Inst. of Technol., Japan
pp. 331-332

A /spl plusmn/1.5 V, 4 MHz low-pass Gm-C filter in CMOS (PDF)

Changsik Yoo , Sch. of Electr. Eng., Seoul Nat. Univ., South Korea
pp. 341-342

Motion adaptive image sensor (PDF)

T. Hamamoto , Dept. of Electr. Eng., Sci. Univ. of Tokyo, Japan
pp. 343-344

Dual-loop digital PLL design for adaptive clock recovery (PDF)

Tae Hun Kim , Dept. of Electr. Eng., Korea Adv. Inst. of Sci. & Technol., Taejon, South Korea
pp. 347-352

High-level estimation techniques for usage in hardware/software co-design (PDF)

J. Henkel , C&C Res. Labs., NEC Res. Inst., Princeton, NJ, USA
pp. 353-360

Loop pipelining in hardware-software partitioning (PDF)

Jinhwan Jeon , Sch. of Electr. Eng., Seoul Nat. Univ., South Korea
pp. 361-366

Hierarchical LVS based on hierarchy rebuilding (PDF)

Wonjong Kim , Dept. of Electron. Eng., Hanyang Univ., Ansan, South Korea
pp. 379-384

Tool capabilities needed for designing 100 MHz interconnects (PDF)

T.A. Schreyer , Archit. Labs., Intel Corp., Hillsboro, OR, USA
pp. 391-395

An analysis on VLSI interconnection considering skin effect (PDF)

T. Mido , Dept. of Electron. Eng., Tokyo Univ., Japan
pp. 403-408

Design of nonlinear switched-current circuits using building block approach (PDF)

X. Zeng , Dept. of Electr. Eng., Fudan Univ., Shanghai, China
pp. 409-414

A new design of double edge triggered flip-flops (PDF)

M. Pedram , Dept. of Electr. Eng. Syst., Univ. of Southern California, Los Angeles, CA, USA
pp. 417-421

Space- and time-efficient BDD construction via working set control (PDF)

Bwolen Yang , Dept. of Comput. Sci., Carnegie Mellon Univ., Pittsburgh, PA, USA
pp. 423-432

Manipulation of *BMDs (PDF)

R. Drechsler , Inst. of Comput. Sci., Albert-Ludwigs-Univ., Freiburg, Germany
pp. 433-438

Decision diagrams for discrete functions: classification and unified interpretation (PDF)

R.S. Stankovic , Dept. of Comput. Sci., Fac. of Electron., Nia, Yugoslavia
pp. 439-446

Reconfigurable systems: a survey (PDF)

T. Miyazaki , NTT Opt. Network Syst. Lab., Atsugi, Japan
pp. 447-452

Reconfigurable systems: activities in Asia and South Pacific (PDF)

H. Amano , Dept. of Comput. Sci., Keio Univ., Yokohama, Japan
pp. 453-457

Asian-Pacific LSI business in the 21st century (PDF)

O. Karatsu , Advanced Telecommunications Research Institute
pp. 459

LSI business of China in 21st century (PDF)

Z.Y. Xu , R&D, Xiamen Microelectron. Integration Technol., China
pp. 461-462

A redundant fault identification algorithm with Exclusive-OR circuit reduction (PDF)

M. Tandai , Gen. Purpose Comput. Div., Hitachi Ltd., Hadano, Japan
pp. 463-468

Interchangeable boolean functions and their effects on redundancy in logic circuits (PDF)

D.K. Das , Dept. of Comput. Sci. & Eng., Jadavpur Univ., Calcutta, India
pp. 469-474

Real time fault injection using logic emulators (PDF)

R. Sedaghat-Maman , Inst. of Microelectron. Syst., Hannover Univ., Germany
pp. 475-479

Integer programming models for optimization problems in test generation (PDF)

J.P. Marques Silva , Cadence Eur. Labs., IST/INESC, Lisbon, Portugal
pp. 481-487

A fast and accurate method of redesigning analog subcircuits for technology scaling (PDF)

S. Funaba , Semicond. & Integrated Circuits Div., Hitachi Ltd., Tokyo, Japan
pp. 489-494

A novel design assistant for analog circuits (PDF)

M. Wolf , Inst. for Meas. Technol. & Electron., Otto-von-Guericke Univ. of Magdeburg, Germany
pp. 495-500

Automatic test generation of linear analog circuits under parameter variations (PDF)

C.-J. R. Shi , Dept. of Electr. & Comput. Eng., Iowa Univ., Iowa City, IA, USA
pp. 501-506

The ensparsed LU decomposition method for large scale circuit transient analysis (PDF)

R. Suda , Dept. of Comput. Sci. & Technol., Nagoya Univ., Japan
pp. 507-512

An incremental placement and global routing algorithm for field-programmable gate arrays (PDF)

N. Togawa , Dept. of Electron., Inf. & Commun. Eng., Waseda Univ., Tokyo, Japan
pp. 519-526

On the optimal sub-routing structures of 2-D FPGA greedy routing architectures (PDF)

Jiaofeng Pan , Dept. of Comput. Sci. & Eng., Chinese Univ. of Hong Kong, Shatin, Hong Kong
pp. 535-540

Power reduction in pipelines (PDF)

S. Parameswaran , Dept. of Comput. Sci. & Electr. Eng., Queensland Univ., Brisbane, Qld., Australia
pp. 545-550

A hybrid power model for RTL power estimation (PDF)

Yi-Min Jiang , Dept. of Electr. & Comput. Eng., California Univ., Santa Barbara, CA, USA
pp. 551-556

Synthesis of power efficient systems-on-silicon (PDF)

D. Kirovski , Dept. of Comput. Sci., California Univ., Los Angeles, CA, USA
pp. 557-562

Air-pressure-model-based fast algorithms for general floorplan (PDF)

T. Izumi , Dept. of Electr. & Electron. Eng., Tokyo Inst. of Technol., Japan
pp. 563-570

Module placement on BSG-structure with pre-placed modules and rectilinear modules (PDF)

S. Nakatake , Dept. of Electr. & Electron. Eng., Tokyo Inst. of Technol., Japan
pp. 571-576

VLSI for multimedia U-NII WLANs (PDF)

N. Weste , Electron. Dept., Macquarie Univ., Sydney, NSW, Australia
pp. 585-587

CMOS image sensors with video compression (PDF)

S. Kawahito , Dept. of Inf. & Comput. Sci., Toyohashi Univ. of Technol., Japan
pp. 595-600
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