Proceedings of the ASP-DAC '99 Asia and South Pacific Design Automation Conference 1999 (Cat. No.99EX198) (PDF)

Organizing Committee (PDF)

International Advisory Committee (PDF)

Steering Committee (PDF)

Welcome to ASP-DAC'99 (PDF)

Welcome to ASP-DAC'99 Exhibition (PDF)

Invitation to ASP-DAC 2000 (PDF)

Technical Program Committee (PDF)

Best Paper Award Candidates (PDF)

University LSI Design Contest Committee (PDF)

University LSI Design Contest Summary (PDF)

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Balanced Multi-Level Multi-Way Partitioning of Large Analog Circuits for Hierarchical Symbolic Analysis (Abstract)

Symmetry Detection for Automatic Analog-Layout Recycling (Abstract)

An SA-Based Nonlinear Function Synthesizer for Linear Analog Integrated Circuits (Abstract)

Relaxed Simulated Tempering for VLSI Floorplan Designs (Abstract)

Slicing Floorplans with Boundary Constraint (Abstract)

Design and Optimization of Power/Ground Network for Cell-Based VLSIs with Macro Cells (Abstract)

An 8b 52MHz Double-Channel CMOS A/D Converter for High-Speed Data Communications (Abstract)

A 10b 50 MHz CMOS A/D Converter for High-Speed Video Applications (Abstract)

The Design of Delay Insensitive Asynchronous 16-bit Microprocessor (Abstract)

An LSI Implementation of an Adaptive Genetic Algorithm with On-The Fly Crossover Operator Selection (Abstract)

Motion Estimator LSI for MPEG2 High Level Standard (Abstract)

A Single-Chip CMOS CCD Camera Interface Circuit with Digitally Controlled AGC (Abstract)

16-bit DSP and System for Baseband / Voiceband Processing of IS-136 Cellular Telephony (Abstract)

Reduced-Order Modelling of Time-Varying Systems (Abstract)

Analysing Forced Oscillators with Multiple Time Scales (Abstract)

Waveform Relaxation of Linear Integral-Differential Equations for Circuit Simulation (Abstract)

A New Technique to Exploit Frequency Domain Latency in Harmonic Balance Simulators (Abstract)

An Efficient Two-Level Partitioning Algorithm for VLSI Circuits (Abstract)

An Efficient Iterative Improvement Technique for VLSI Circuit Partitioning Using Hybrid Bucket Structures (Abstract)

A Clustering Based Linear Ordering Algorithm for K-Way Spectral Partitioning (Abstract)

Faster and Better Spectral Algorithms for Multi-Way Partitioning (Abstract)

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VCO Jitter Simulation and Its Comparison With Measurement (Abstract)

Enhancing the Efficiency of Reduction of Large RC networks By Pole Analysis via Congruence Transformations (Abstract)

The Hierarchical h-Adaptive 3-D Boundary Element Computation of VLSI Interconnect Capacitance (Abstract)

Interconnect Delay Estimation Models for Synthesis and Design Planning (Abstract)

An Analytical Delay Model for SRAM-Based FPGA Interconnections (Abstract)

Timing-Driven Bipartitioning with Replication Using Iterative Quadratic Programming (Abstract)

An Integrated Battery-Hardware Model for Portable Electronics (Abstract)

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Design Method of MTCMOS Power Switch for Low-Voltage High-Speed LSIs (Abstract)

A New Single-Clock Flip-Clop for Half-Swing Clocking (Abstract)

Optimal Evaluation Clocking of Self-Resetting Domino Pipelines (Abstract)

Clock Period Minimization of Semi-Synchronous Circuits by Gate-Level Delay Insertion (Abstract)

A Performance-Driven I/O Pin Routing Algorithm (Abstract)

An Automatic Router for the Pin Grid Array Package (Abstract)

Crosstalk Reduction by Transistor Sizing (Abstract)

A Technology-Independent Methodology of Placement Generation for Analog Circuit (Abstract)

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Technnology Mapping for Low Power (Abstract)

An Efficient Aopproach to Constrained Via Minimization for Two-Layer VLSI Routing (Abstract)

Automatic Constraint Transformation with Integrated Parameter Space Exploration in Analog System Synthesis (Abstract)

Node Sampling Technique to Speed Up Probability-Based Power Estimation Methods (Abstract)

Acceleration of Linear Block Code Evaluations Using New Reconfigurable Computing Approach (Abstract)

A New Numerical Method for Transient Noise Analysis of Nonlinear Circuits (Abstract)

Low Power CMOS Off-Chip Drivers with Slew-rate Difference (Abstract)

Benchmark Circuits Improve the Quality of a Standard Cell Library (Abstract)

Formal Design Verification for Correctness of Pipelined Microprocessors with Out-of-order Instruction Execution (Abstract)

Solving the Rectangular Packing Problem by an Adaptive GA Based on Sequence-Pair (Abstract)

Hazard-Free Synthesis and Decomposition of Asynchronous Circuits (Abstract)

Hierarchical Floorplan Design on the Internet (Abstract)

A Scheduling Method for Synchronous Communication in the Bach Hardware Compiler (Abstract)

Electronics Development of Silicon Microdisplay for Virtual Reality Applications (Abstract)

High-Speed and Low-Power Real-Time Programmable Video Multi-Processor for MPEG-2 Multimedia Chip on 0.6μm TLM CMOS Technology (Abstract)

A Scalable Pipelined Architecture for Separable 2-D Discrete Wavelet Transform (Abstract)

A New Pipelined Architecture for Fuzzy Color Correction (Abstract)

Watermarking Layout Topologies (Abstract)

Optimal Wire Shape with Consideration of Coupling Capacitance under Elmore Delay Model (Abstract)

New Multilevel and Hierarchical Algorithms for Layout Density Control (Abstract)

Function Smoothing with Applications to VLSI Layout (Abstract)

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Layout-based Logic Decomposition for Timing Optimization (Abstract)

Timing Optimization of Logic Network Using Gate Duplication (Abstract)

Model Order Reduction of Large Circuits Using Balanced Truncation (Abstract)

Optimization of Linear Placements for Wirelength Minimization with Free Sites (Abstract)

A New Global Routing Algorithm Independent Of Net Ordering (Abstract)

A Timing-Driven Block Placer Based on Sequence Pair Model (Abstract)

Roadmap organization and activities in Japan (PDF)

EDA Roadmap in Japan (PDF)

A US/Japan comparison of design/EDA capabilities (PDF)

VCDS: virtual core based design system (PDF)

Embedded tutorial: hardware/software codesign (PDF)

Microprocessor technologies for the 21st century (PDF)

Package market segments and design challenges (PDF)

Electrical design and design automation for packaging (PDF)

Thermal/mechanical design and design automation for packaging (PDF)

Chip-package codesign-challenges and directions (PDF)

Design re-use: where is the productivity going to come from? (PDF)

Estimation of Peak Current through CMOS VLSI Circuit Supply Lines (Abstract)

Power Consumption in XOR-Based Circuits (Abstract)

Exploiting Don't Caers During Data Sequencing using Genetic Algorithms (Abstract)

An Efficient Structural Approach to Board Interconnect Diagnosis (Abstract)

On the Testing Quality of Random and Pseudo-random Sequences for Permanent and Intermittent Faults (Abstract)

Combining GAs and Symbolic Methods for High Quality Tests of Sequential Circuits (Abstract)

Formal Verification Method for Combinatorial Circuits at High Level Design (Abstract)

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Minimization of Free BDDs (Abstract)

Application Driven Variable Reordering and an Example Implementation in Reachability Analysis (Abstract)

Realization of Regular Ternary Logic Functions (Abstract)

A Hardware/Software Partitioning Algorithm for Processor Cores of Digital Signal Processing (Abstract)

Generation of Interpretive and Compiled Instruction Set Simulators (Abstract)

Combining Speculative Execution and Conditional Resource Sharing to Efficiently Schedule Conditional Behaviors (Abstract)

Fast Instruction Cache Simulation Strategies in a Hardware/Software Co-Design Environment (Abstract)

A Multi-Level FPGA Synthesis Method Supporting HDL Debugging for Emulation-Based Designs (Abstract)

A Genetic Algorithm based Approach for Multi-Objective Data-Flow Graph Optimization (Abstract)

Fast Boolean Matching Under Permutation Using Representative (Abstract)

FSM Modeling of Synchronous VHDL Design for Symbolic Model Checking (Abstract)

Conference Author Index (PDF)