[Front cover] (PDF)

[Copyright notice] (PDF)

Table of contents (PDF)

Title page i (Abstract)

Title Page iii (PDF)

Message from the ASAP '09 General and Technical Program Chairs (PDF)

Organizing Committee (PDF)

Division Unit for Binary Integer Decimals (Abstract)

A Combined Decimal and Binary Floating-Point Multiplier (Abstract)

Parallel Prefix Ling Structures for Modulo 2^n-1 Addition (Abstract)

A FPGA-based Parallel Architecture for Scalable High-Speed Packet Classification (Abstract)

Implementing a Highly Parameterized Digital PIV System on Reconfigurable Hardware (Abstract)

Improving VLIW Processor Performance Using Three-Dimensional (3D) DRAM Stacking (Abstract)

Specialization of the Cell SPE for Media Applications (Abstract)

A Massively Parallel Coprocessor for Convolutional Neural Networks (Abstract)

An FPGA-based Parallel Hardware Architecture for Real-Time Face Detection Using a Face Certainty Map (Abstract)

Accelerating a Virtual Ecology Model with FPGAs (Abstract)

Parallelized Architecture of Multiple Classifiers for Face Detection (Abstract)

Design and Implementation of a Radix-4 Complex Division Unit with Prescaling (Abstract)

A Low Power High Performance Radix-4 Approximate Squaring Circuit (Abstract)

A Novel Processor Architecture for McEliece Cryptosystem and FPGA Platforms (Abstract)

An Input Triggered Polymorphic ASIC for H.264 Decoding (Abstract)

A Power-Scalable Switch-Based Multi-processor FFT (Abstract)

MSA-CUDA: Multiple Sequence Alignment on Graphics Processing Units with CUDA (Abstract)

Parallel Discrete Event Simulation of Molecular Dynamics Through Event-Based Decomposition (Abstract)

NeMo: A Platform for Neural Modelling of Spiking Neurons Using GPUs (Abstract)

Constraint-Driven Instructions Selection and Application Scheduling in the DURASE system (Abstract)

A System Framework for the Design of Embedded Software Targeting Heterogeneous Multi-core SoCs (Abstract)

[Publisher's information] (PDF)

Evaluating Various Branch-Prediction Schemes for Biomedical-Implant Processors (Abstract)

Low-Power ASIP Architecture Exploration and Optimization for Reed-Solomon Processing (Abstract)

Scalar Processing Overhead on SIMD-Only Architectures (Abstract)

Integral Parallel Architecture & Berkeley's Motifs (Abstract)

Application Specific Transistor Sizing for Low Power Full Adders (Abstract)

Reconfigurable SWP Operator for Multimedia Processing (Abstract)

Filtering Global History: Power and Performance Efficient Branch Predictor (Abstract)

Efficient Implementation of Carry-Save Adders in FPGAs (Abstract)

Acceleration of Multiresolution Imaging Algorithms: A Comparative Study (Abstract)

A High-Performance Hardware Architecture for Spectral Hash Algorithm (Abstract)

P3FSM: Portable Predictive Pattern Matching Finite State Machine (Abstract)

Run-Time Detection of Malwares via Dynamic Control-Flow Inspection (Abstract)

A 16-context Optically Reconfigurable Gate Array (Abstract)

Mapping Parallel FFT Algorithm onto SmartCell Coarse-Grained Reconfigurable Architecture (Abstract)

An Area-Efficient LDPC Decoder Architecture and Implementation for CMMB Systems (Abstract)

Author Index (PDF)