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Proceedings of International Conference on Application Specific Array Processors (ASAP '93) (1993)
Venice, Italy
Oct. 25, 1993 to Oct. 27, 1993
ISSN: 1063-6862
ISBN: 0-8186-3492-8
TABLE OF CONTENTS

Communication-minimal mapping of uniform loop nests onto distributed memory architectures (PDF)

A. Darte , Lab. LIP-IMAG, Ecole Normale Superieure de Lyon, France
Y. Robert , Lab. LIP-IMAG, Ecole Normale Superieure de Lyon, France
pp. 1-14

The Xor embedding: An embedding of hypercubes onto rings and toruses (PDF)

A. Gonzalez , Dept. d'Arquitectura de Computadors, Univ. Politecnica de Catalunya, Barcelona, Spain
M. Valero-Garcia , Dept. d'Arquitectura de Computadors, Univ. Politecnica de Catalunya, Barcelona, Spain
pp. 15-28

Resource constrained scheduling of uniform algorithm (PDF)

L. Thiele , Saarland Univ., Saarbrucken, Germany
pp. 29-40

Mapping algorithms onto a multiple-chip data-driven array (PDF)

B. Mendelson , IBM Israel - Sci. & Technol., Haifa, Israel
I. Koren , IBM Israel - Sci. & Technol., Haifa, Israel
pp. 41-52

Scheduling partitioned algorithms on processor arrays with limited communication supports (PDF)

W.H. Chou , Dept. of Electr. Eng., Princeton Univ., NJ, USA
S.Y. Kung , Dept. of Electr. Eng., Princeton Univ., NJ, USA
pp. 53-64

Parallel processing architectures for rank order and stack filters (PDF)

L.E. Lucke , Dept. of Electr. Eng., Minnesota Univ., Minneapolis, MN, USA
K.K. Parhi , Dept. of Electr. Eng., Minnesota Univ., Minneapolis, MN, USA
pp. 65-76

A novel framework for multi-rate scheduling in DSP applications (PDF)

R. Govindarajan , Dept. of Electr. Eng., McGill Univ., Montreal, Que., Canada
G.R. Gao , Dept. of Electr. Eng., McGill Univ., Montreal, Que., Canada
pp. 77-88

Efficient scalable architectures for Viterbi decoders (PDF)

S. Bitterlich , Aachen Univ. of Technol., Germany
H. Meyr , Aachen Univ. of Technol., Germany
pp. 89-100

Subband filtering: Cordic modulation and systolic quadrature mirror filter tree (PDF)

E.F. Deprettere , Dept. of Electr. Eng., Delft Univ. of Technol., Netherlands
R. Heusdens , Dept. of Electr. Eng., Delft Univ. of Technol., Netherlands
pp. 109-123

On synthesizing application-specific array architectures from behavioral specifications (PDF)

P.M.R. Jensen , Dept. of Commun. Technol., Aalborg Univ., Denmark
K. Hermansen , Dept. of Commun. Technol., Aalborg Univ., Denmark
pp. 124-127

A simple expert system for the reasoning of systolic designs (PDF)

N. Ling , Dept. of Comput. Eng., Santa Clara Univ., CA, USA
pp. 128-131

RELACS for systolic programming (PDF)

F. Raimbault , IRISA, Rennes, France
D. Lavenier , IRISA, Rennes, France
pp. 132-135

Data flow graphs granularity for overhead reduction within a PE in multiprocessor systems (PDF)

M. Coli , Dipartimento di Ingegneria Elettronica, Rome Univ., Italy
P. Palazzari , Dipartimento di Ingegneria Elettronica, Rome Univ., Italy
pp. 136-139

A massively parallel diagonal-fold array processor (PDF)

G.G. Pechanek , IBM, Research Triangle Park, NC, USA
J.G. Delgado-Frias , IBM, Research Triangle Park, NC, USA
pp. 140-143

Response-pipelined CAM chips - Building blocks for large associated arrays (PDF)

K. Ghose , Dept. of Comput. Sci., State Univ. of New York, Binghamton, NY, USA
pp. 144-147

An array-processor based architecture for classification problems (PDF)

A. Bellettini , Bologna Univ., Italy
A. Ferrari , Bologna Univ., Italy
R. Guerrieri , Bologna Univ., Italy
G. Baccarani , Bologna Univ., Italy
pp. 148-151

Realization of a real time phasecorrelation chipset used in a hierarchical two step HDTV motion vector estimator (PDF)

K. Muller , Institut fuer Mikroelektronik, TU-Berlin, Germany
F. Schirrmeister , Institut fuer Mikroelektronik, TU-Berlin, Germany
C. Reventlow , Institut fuer Mikroelektronik, TU-Berlin, Germany
D. Siebert , Institut fuer Mikroelektronik, TU-Berlin, Germany
J. Reimers , Institut fuer Mikroelektronik, TU-Berlin, Germany
C. Stoffers , Institut fuer Mikroelektronik, TU-Berlin, Germany
pp. 152-155

Mapping arbitrary projections for volume rendering onto an array processor (PDF)

C.H.J. Ju , Dept. of Electr. Eng., Princeton Univ., NJ, USA
H.H. Taylor , Dept. of Electr. Eng., Princeton Univ., NJ, USA
pp. 160-163

Processing of variable size images on a cellular array: Performance analysis with the Abingdon Cross Benchmark (PDF)

M. Piccardi , Dipartimento di Elettronica, Inf. e Sistemistica, Bologna Univ., Italy
L. De Stefano , Dipartimento di Elettronica, Inf. e Sistemistica, Bologna Univ., Italy
R. Cucchiara , Dipartimento di Elettronica, Inf. e Sistemistica, Bologna Univ., Italy
T.S. Cinotti , Dipartimento di Elettronica, Inf. e Sistemistica, Bologna Univ., Italy
pp. 172-175

Matrix-matrix multiplications and fault tolerance on hypercube multiprocessors (PDF)

Y.-R. Leu , Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan
I.-Y. Chen , Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan
pp. 176-180

Reconfigurable hardware for molecular biology computing systems (PDF)

E. Lemoine , CNRS & Univ. Montpellier II, France
pp. 184-187

Systolic design of a new finite field division/inverse algorithm (PDF)

R. Conway , Dept. of Electron. and Comput. Eng., Limerick Univ., Ireland
J. Nelson , Dept. of Electron. and Comput. Eng., Limerick Univ., Ireland
pp. 188-191

Mapping Monte Carlo-Metropolis algorithm onto a double ring architecture (PDF)

G. Danese , Dipartimento di Inf. e Sistemistica, Pavia, Italy
I. De Lotto , Dipartimento di Inf. e Sistemistica, Pavia, Italy
D. Dotti , Dipartimento di Inf. e Sistemistica, Pavia, Italy
D. Lanterna , Dipartimento di Inf. e Sistemistica, Pavia, Italy
F. Leporati , Dipartimento di Inf. e Sistemistica, Pavia, Italy
R. Lombardi , Dipartimento di Inf. e Sistemistica, Pavia, Italy
S. Romano , Dipartimento di Inf. e Sistemistica, Pavia, Italy
pp. 192-195

An application specific processor for implementing stack filters (PDF)

B.K. Kar , Dept. of Electr. & Comput. Eng., Massachusetts Univ., Amherst, MA, USA
R.C.K. Kumar , Dept. of Electr. & Comput. Eng., Massachusetts Univ., Amherst, MA, USA
pp. 196-199

Low-power polygon renderer for computer graphics (PDF)

W.-C. Tan , Comput. Syst. Lab., Stanford Univ., CA, USA
T.-Y. Meng , Comput. Syst. Lab., Stanford Univ., CA, USA
pp. 200-213

Volume rendering by wavefront architecture (PDF)

S.-H. Lin , Dept. of Electr. Eng., Princeton Univ., NJ, USA
S. Kung , Dept. of Electr. Eng., Princeton Univ., NJ, USA
pp. 214-225

Time-optimal visibility-related algorithms on meshes with multiple broadcasting (PDF)

D. Bhagavathi , Dept. of C.S., Old Dominion Univ., Norfolk, VA, USA
V. Bokka , Dept. of C.S., Old Dominion Univ., Norfolk, VA, USA
H. Gurla , Dept. of C.S., Old Dominion Univ., Norfolk, VA, USA
S. Olariu , Dept. of C.S., Old Dominion Univ., Norfolk, VA, USA
J.L. Schwing , Dept. of C.S., Old Dominion Univ., Norfolk, VA, USA
I. Stojmenovic , Dept. of C.S., Old Dominion Univ., Norfolk, VA, USA
J. Zhang , Dept. of C.S., Old Dominion Univ., Norfolk, VA, USA
pp. 226-237

A real-time systolic algorithm for on-the-fly hidden surface removal (PDF)

T. Risset , Ecole Normale Superieure de Lyon, France
S.W. Song , Ecole Normale Superieure de Lyon, France
pp. 238-249

An efficient algorithm for image-template product on SIMD mesh connected computers (PDF)

H. Shi , Dept. of Comput. & Inf. Sci., Florida Univ., Gainesville, FL, USA
G.X. Ritter , Dept. of Comput. & Inf. Sci., Florida Univ., Gainesville, FL, USA
J.N. Wilson , Dept. of Comput. & Inf. Sci., Florida Univ., Gainesville, FL, USA
pp. 250-260

A period-processor-time-minimal schedule for cubical mesh algorithms (PDF)

C. Scheiman , Dept. of Comput. Sci., California Univ., Santa Barbara, CA, USA
P. Cappello , Dept. of Comput. Sci., California Univ., Santa Barbara, CA, USA
pp. 261-272

I/O data management on SIMD systolic arrays (PDF)

P. Frison , IRISA, Rennes, France
D. Lavenier , IRISA, Rennes, France
F. Raimbault , IRISA, Rennes, France
pp. 273-284

Optimum vectorization of scalable synchronous dataflow graphs (PDF)

S. Ritz , Aachen Univ. of Technol., Germany
M. Pankert , Aachen Univ. of Technol., Germany
V. Zivojinovic , Aachen Univ. of Technol., Germany
H. Meyr , Aachen Univ. of Technol., Germany
pp. 285-296

A new formulation of the mapping conditions for the synthesis of linear systolic arrays (PDF)

J. Xue , Sch. of Electr. & Electron. Eng., Nanyang Technol. Univ., Singapore
pp. 297-308

The PAPRICA SIMD array: Critical reviews and perspectives (PDF)

F. Gregoretti , Dip. di Elettronica, Politecnico di Torino, Italy
C. Sansoe , Dip. di Elettronica, Politecnico di Torino, Italy
pp. 309-320

Formal descriptions, semantics and verification of VLSI array processors (PDF)

Z. Zhou , Dept. of Electron. & Comput. Eng., Massachusetts Univ., Amherst, MA, USA
W. Burleson , Dept. of Electron. & Comput. Eng., Massachusetts Univ., Amherst, MA, USA
pp. 321-332

An application-specific array architecture for feedforward with backpropagation ANNs (PDF)

Q.M. Malluhi , Center for Adv. Comput. Studies, Univ. of Southwestern Louisiana, Lafayette, LA, USA
M.A. Bayoumi , Center for Adv. Comput. Studies, Univ. of Southwestern Louisiana, Lafayette, LA, USA
T.R.N. Rao , Center for Adv. Comput. Studies, Univ. of Southwestern Louisiana, Lafayette, LA, USA
pp. 333-344

GENES IV: A bit-serial processing element for a built-model neural-network accelerator (PDF)

P. Ienne , Swiss Federal Inst. of Technol., Lausanne, Switzerland
M.A. Viredaz , Swiss Federal Inst. of Technol., Lausanne, Switzerland
pp. 345-356

A fast, storage-efficient parallel sorting algorithm (PDF)

R.P. Brent , Comput. Sci. Lab., Australian Nat. Univ., Canberra, ACT, Australia
A. Tridgell , Comput. Sci. Lab., Australian Nat. Univ., Canberra, ACT, Australia
pp. 369-379

Implementation of large neural associative memories by massively parallel array processors (PDF)

A. Strey , Dept. of Neural Inf. Process., Ulm Univ., Germany
pp. 357-368

A practical constant time sorting network (PDF)

R. Lin , Dept. of Comput. Sci., State Univ. of New York, Genesco, NY, USA
S. Olariu , Dept. of Comput. Sci., State Univ. of New York, Genesco, NY, USA
pp. 380-391

Multi-rate transformation of directional affine recurrence equations (PDF)

Y. Zheng , Dept. of Electr. & Comput. Eng., Oregon State Univ., Corvallis, OR, USA
S. Kiaei , Dept. of Electr. & Comput. Eng., Oregon State Univ., Corvallis, OR, USA
pp. 392-403

An algorithm for accurate data dependence test (PDF)

Z. Xing , Center for Adv. Comput. Studies, Univ. of Southwestern Louisiana, Lafayette, LA, USA
W. Shang , Center for Adv. Comput. Studies, Univ. of Southwestern Louisiana, Lafayette, LA, USA
pp. 404-415

Synthesis of dedicated SIMD processors (PDF)

M. Auguin , CNRS, Univ. de Nice Sophia-Antipolis, Nice, France
F. Boeri , CNRS, Univ. de Nice Sophia-Antipolis, Nice, France
C. Carriere , CNRS, Univ. de Nice Sophia-Antipolis, Nice, France
G. Menez , CNRS, Univ. de Nice Sophia-Antipolis, Nice, France
pp. 416-427

Efficient exploration of nonuniform space-time transformations for optimal systolic array synthesis (PDF)

D.G. Baltus , Dept. of Electr. Eng. & Comput. Sci., MIT, Cambridge, MA, USA
J. Allen , Dept. of Electr. Eng. & Comput. Sci., MIT, Cambridge, MA, USA
pp. 428-441

Node merging: A transformation on bit-level dependence graphs for efficient VLSI array design (PDF)

B. Jung , Dept. of Electr. & Comput. Eng., Massachusetts Univ., Amherst, MA, USA
W. Burleson , Dept. of Electr. & Comput. Eng., Massachusetts Univ., Amherst, MA, USA
pp. 442-453

Digit systolic algorithms for fine-grain architectures (PDF)

C. Nagendra , Dept. of Comput. Sci. & Eng., Pennsylvania State Univ., University Park, PA, USA
R.M. Owens , Dept. of Comput. Sci. & Eng., Pennsylvania State Univ., University Park, PA, USA
M.J. Irwin , Dept. of Comput. Sci. & Eng., Pennsylvania State Univ., University Park, PA, USA
pp. 466-477

Reduced area multipliers (PDF)

K.A.C. Bickerstaff , Dept. of Electr. & Comput. Eng., Texas Univ., Austin, TX, USA
M. Schulte , Dept. of Electr. & Comput. Eng., Texas Univ., Austin, TX, USA
E.E. Swartzlander , Dept. of Electr. & Comput. Eng., Texas Univ., Austin, TX, USA
pp. 478-489

Systolic normalization of rational numbers (PDF)

T. Jebelean , RISC-LINZ, Austria
pp. 502-513

VLSI array synthesis for polynomial GCD computation (PDF)

Y. Jeong , Dept. of Electr. & Comput. Eng., Massachusetts Univ., Amherst, MA, USA
W. Burleson , Dept. of Electr. & Comput. Eng., Massachusetts Univ., Amherst, MA, USA
pp. 536-547

An optimal algo-tech-cuit for the knapsack problem (PDF)

R. Andonov , IRISA, Rennes, France
S. Rajopadhye , IRISA, Rennes, France
pp. 548-559

Efficient architecture of a programmable block matching processor (PDF)

L. De Vos , Siemens AG, Munich, Germany
M. Schobinger , Siemens AG, Munich, Germany
pp. 560-571

A 1D linearly expandable interconnection network performance analysis (PDF)

D. Houzet , IRIT-ENSEEIHT, Toulouse, France
K. Fatni , IRIT-ENSEEIHT, Toulouse, France
pp. 572-582

A CAD tool for electromagnetic simulation on the associative string processor (PDF)

D.P. Rodohan , Brunel Univ., Uxbridge, UK
S.R. Saunders , Brunel Univ., Uxbridge, UK
pp. 583-592
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