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Proceedings of the International Conference on Application Specific Array Processors (1991)
Barcelona, Spain
Sept. 2, 1991 to Sept. 4, 1991
ISBN: 0-8186-9237-5
TABLE OF CONTENTS

Pipelining and transposing heterogeneous array circuits (PDF)

W.W.C. Luk , Oxford Univ. Comput. Lab., UK
pp. 263-277

High speed implementation of 1-D and 2-D morphological operations (PDF)

J. Vlontzos , Siemens Corporate Res., Princeton, NJ, USA
pp. 249-262

CAPMA: a content-addressable pattern match architecture for production systems (PDF)

Chie Dou , Chung Shan Inst. of Sci. & Technol., Taoyuan, Taiwan
Shao-Ming Wu , Chung Shan Inst. of Sci. & Technol., Taoyuan, Taiwan
pp. 236-248

Parallel array architectures for motion estimation (PDF)

T.H.-Y. Meng , Comput. Systs. Lab., Stanford Univ., CA, USA
A.C. Hung , Comput. Systs. Lab., Stanford Univ., CA, USA
pp. 214-235

Parallel strong orientation on a mesh connected computer (PDF)

M. Schimmler , Inst. fur Informatik und praktische Math., Kiel, Germany
pp. 199-211

Parallel implementations of discrete relaxation technique on fixed size processor arrays (PDF)

Wei-Ming Lin , Dept. of EE-Systs., Univ. of Southern California, Los Angeles, CA, USA
V. Prasanna , Dept. of EE-Systs., Univ. of Southern California, Los Angeles, CA, USA
pp. 184-198

Biological information signal processor (PDF)

E. Chow , California Inst. of Technol., Pasadena, CA, USA
T. Hunkapiller , California Inst. of Technol., Pasadena, CA, USA
J. Peterson , California Inst. of Technol., Pasadena, CA, USA
pp. 144-160

The Arithmetic Cube: error analysis and simulation (PDF)

M. Vishwanath , Dept. of Comput. Sci., Pennsylvania State Univ., University Park, PA, USA
R.M. Owens , Dept. of Comput. Sci., Pennsylvania State Univ., University Park, PA, USA
M.J. Irwin , Dept. of Comput. Sci., Pennsylvania State Univ., University Park, PA, USA
pp. 129-143

A wave digital filter three-port adaptor with fine grained pipelining (PDF)

R. Jit Singh , Dept. of Elect. & Electron. Eng., Queen's Univ. of Belfast, UK
J.V. McCanny , Dept. of Elect. & Electron. Eng., Queen's Univ. of Belfast, UK
pp. 116-128

Mapping FIR filtering on systolic rings (PDF)

A. Varvitsiotis , Dept. of Electr. Eng., Nat. Tech. Univ. of Athens, Greece
pp. 87-101

Mapping different node types of dependence graphs into the same processing element (PDF)

U. Vehlies , Lab. fur Informationstechnol., Hannover Univ., Germany
pp. 72-86

Transformation of systolic algorithms for interleaving partitions (PDF)

A. Fernandez , Dept. d'Arquitectura de Computadors, Univ. Politecnica de Catalunya, Barcelona, Spain
J.M. Llaberia , Dept. d'Arquitectura de Computadors, Univ. Politecnica de Catalunya, Barcelona, Spain
J.J. Navarro , Dept. d'Arquitectura de Computadors, Univ. Politecnica de Catalunya, Barcelona, Spain
M. Valero-Garcia , Dept. d'Arquitectura de Computadors, Univ. Politecnica de Catalunya, Barcelona, Spain
pp. 56-71

The systematic design of a motion estimation array architecture (PDF)

J. Rosseel , IMEC v.z.w., Leuven, Belgium
F. Catthoor , IMEC v.z.w., Leuven, Belgium
H. De Man , IMEC v.z.w., Leuven, Belgium
pp. 40-54

A defect tolerant systolic array implementation for real time image processing (PDF)

V. Hecht , Lab. fur Informationstechnol., Hannover Univ., Germany
K. Ronner , Lab. fur Informationstechnol., Hannover Univ., Germany
P. Pirsch , Lab. fur Informationstechnol., Hannover Univ., Germany
pp. 25-39

The case for application specific computing (PDF)

E. Swartzlander , Dept. of Electr. & Comput. Eng., Texas Univ., Austin, TX, USA
pp. 2-9

Systolic architecture for adaptive eigenstructure decomposition based on simultaneous iteration method (PDF)

S. Erlich , California Univ., Los Angeles, CA, USA
K. Yao , California Univ., Los Angeles, CA, USA
pp. 485-495

A systolic algorithm for the triangular Stein equation (PDF)

J.L. Hueso , Univ. Politecnica de Valencia, Spain
G. Martinez , Univ. Politecnica de Valencia, Spain
V. Hernandez , Univ. Politecnica de Valencia, Spain
pp. 473-484

A modular systolic 2-D torus for the general knapsack problem (PDF)

R. Andonov , Center for Inf. & Comput. Technol., Sophia, Bulgaria
pp. 458-472

Fast generation of long sorted runs for sorting a large file (PDF)

Yen-Chun lin , Dept. of Electron. Eng., Taiwan Inst. of Technol., Taipei, Taiwan
Yu-Ho Cheng , Dept. of Electron. Eng., Taiwan Inst. of Technol., Taipei, Taiwan
pp. 445-456

GFLOPS: a general flexible linearly organized parallel structure for images (PDF)

D. Houzet , IRIT, Toulouse, France
J.-L. Basille , IRIT, Toulouse, France
J.-Y. Latil , IRIT, Toulouse, France
pp. 431-444

A 40 megasample IIR filter chip (PDF)

O.C. McNally , Dept. of Electr. & Electron. Eng., Queen's Univ., Belfast, UK
J.V. McCanny , Dept. of Electr. & Electron. Eng., Queen's Univ., Belfast, UK
R.F. Woods , Dept. of Electr. & Electron. Eng., Queen's Univ., Belfast, UK
pp. 416-430

A design method for on-line reconfigurable array processors (PDF)

J. Franzen , Lab. fur Informationstechnol., Hannover Univ., Germany
pp. 387-401

Synthesizing systolic arrays: some recent developments (PDF)

A. Darte , Lab. de l'Informatique du Parallelisme, Ecole Normale Superieure de Lyon, France
T. Risset , Lab. de l'Informatique du Parallelisme, Ecole Normale Superieure de Lyon, France
Y. Robert , Lab. de l'Informatique du Parallelisme, Ecole Normale Superieure de Lyon, France
pp. 372-386

Consistency in dataflow graphs (PDF)

E.A. Lee , Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
pp. 355-369

Automatic formal verification of systolic array designs (PDF)

Nam Ling , Dept. of Comput. Eng., Santa Clara Univ., CA, USA
Fuyau Lin , Dept. of Comput. Eng., Santa Clara Univ., CA, USA
T. Shih , Dept. of Comput. Eng., Santa Clara Univ., CA, USA
R. Davis , Dept. of Comput. Eng., Santa Clara Univ., CA, USA
pp. 338-354

Synthesis of systolic arrays by equation transformations (PDF)

C. Dezan , IRISA, Rennes, France
E. Gautrin , IRISA, Rennes, France
H. Le Verge , IRISA, Rennes, France
P. Quinton , IRISA, Rennes, France
Y. Saouter , IRISA, Rennes, France
pp. 324-337

A TSP engine for performing tabu search (PDF)

V. Karamcheti , Dept. of Electr. & Comput. Eng., Texas Univ., Austin, TX, USA
M. Malek , Dept. of Electr. & Comput. Eng., Texas Univ., Austin, TX, USA
pp. 309-321

Uniform but non-local DAGS: a trade-off between pure systolic and SIMD solutions (PDF)

T. Risset , Lab. de l'Inf. du Parallelisme LIP-IMAG, Ecole Normale Superieure de Lyon, France
Y. Robert , Lab. de l'Inf. du Parallelisme LIP-IMAG, Ecole Normale Superieure de Lyon, France
pp. 296-308

A decoupled access/execute processor for matrix algorithms: architecture and programming (PDF)

J.H. Moreno , Dept. de Ingeneria Electrica, Concepcion Univ., Chile
M.E. Figueroa , Dept. de Ingeneria Electrica, Concepcion Univ., Chile
pp. 281-295
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