Calculus of space-optimal mappings of systolic algorithms on processor arrays (PDF)

A processor-time minimal systolic array for transitive closure (PDF)

Systolic array implementation of nested loop programs (PDF)

The bit-serial systolic back-projection engine (BSSBPE) (PDF)

A database machine based on surrogate files (PDF)

Systolic architectures for decoding Reed-Solomon codes (PDF)

Mapping high-dimension wavefront computations to silicon (PDF)

Systolic architecture for 2-D rank order filtering (PDF)

Scheduling affine parameterized recurrences by means of (PDF)

The Logic Description Generator (PDF)

Recursive algorithms for AR spectral estimation and their array realizations (PDF)

Analysing parametrised designs by non-standard interpretation (PDF)

Systolic VLSI compiler (SVC) for high performance vector quantisation chips (PDF)

Extensions to linear mapping for regular arrays with complex processing elements (PDF)

Design of run-time fault-tolerant arrays of self-checking processing elements (PDF)

GRAPE: a special-purpose computer for N-body problems (PDF)

Building blocks for a new generation of application specific computing systems (PDF)

Reconfigurable vector register windows for fast matrix computation on the orthogonal multiprocessor (PDF)

Massively parallel architecture: application to neural net emulation and image reconstruction (PDF)

A real-time software programmable processor for HDTV and stereo scope signals (PDF)

Mapping algorithms onto the TUT cellular array processor (PDF)

A 3-D wafer scale architecture for early vision processing (PDF)

Algorithmic mapping of neural network models onto parallel SIMD machines (PDF)

Implementation of systolic algorithms using pipelined functional units (PDF)

Array processing on finite polynomial rings (PDF)

The RAP: a ring array processor for layered network calculations (PDF)

Linear arrays for residue mappers (PDF)

A fault-tolerant two-dimensional sorting network (PDF)

Channel complexity analysis for reconfigurable VLSI/WSI processor arrays (PDF)

Digit-serial DSP architectures (PDF)

PASIC. A sensor/processor array for computer vision (PDF)

An analog VLSI array processor for classical and connectionist AI (PDF)

Systolic two-port adaptor for high performance wave digital filtering (PDF)

An improved multilayer neural model and array processor implementation (PDF)

Reconfiguration of FFT arrays: a flow-driven approach (PDF)

Towards the automated design of application specific array processors (ASAPs) (PDF)

Fault-tolerant array processors using N-and-half-track switches (PDF)

Domain flow and streaming architectures (PDF)

An improved systolic extended Euclidean algorithm for Reed-Solomon decoding: design and implementation (PDF)

Digit-serial VLSI microarchitecture (PDF)

CMOS VLSI Lukasiewicz logic arrays (PDF)

Dynamic systolic associative memory chip (PDF)

ASP modules: building-blocks for application-specific massively parallel processors (PDF)

Designing specific systolic arrays with the API15C chip (PDF)

A prototype for a fault tolerant parallel signal processor (PDF)

Byte-serial convolvers (PDF)

A VLSI architecture for simplified arithmetic Fourier transform algorithm (PDF)

Fine-grain system architectures for systolic emulation of neural algorithms (PDF)

Programming environment for a line processor-SYMPATI-2 (PDF)

A feedback concentrator for the Image Understanding Architecture (PDF)

A design methodology for fixed-size systolic arrays (PDF)

A formal design methodology for parallel architectures (PDF)

A multiple-level heterogeneous architecture for image understanding (PDF)

Application specific VLSI architectures based on De Bruijn graphs (PDF)

A graph-based approach to map matrix algorithms onto local-access processor arrays (PDF)

Application-specific coprocessor computer architecture (PDF)

Embedding pyramids in array processors with pipelined busses (PDF)

Implementation of ANN on RISC processor array (PDF)

Systolic-based computing machinery for radar signal processing studies (PDF)

A systolic array for nonlinear adaptive filtering and pattern recognition (PDF)

Parallel algorithm for traveling salesman problem on SIMD machines using simulated annealing (PDF)

The design of a high-performance scalable architecture for image processing applications (PDF)

Testing a motion estimator array (PDF)

Spacetime-minimal systolic architectures for Gaussian elimination and the algebraic path problem (PDF)

Two-level pipelined implementation of systolic block Householder transformation with application to RLS algorithm (PDF)

Bit-level systolic algorithm for the symmetric eigenvalue problem (PDF)

A practical runtime test method for parallel lattice-gas automata (PDF)

A systolic array programming language (PDF)

Proceedings of the International Conference on Application Specific Array Processors (Cat. No.90CH2920-7) (PDF)