Proceedings of the International Conference on Systolic Arrays (Cat. No.88CH2603-9) (PDF)

Systolic array for 2-D adaptive beamforming (PDF)

An efficient systolic array for MVDR beamforming (PDF)

Implementation of synthetic aperture radar algorithms on a systolic/cellular architecture (PDF)

Efficient feature extractions by uniform structure threshold logic arrays (PDF)

Architecture of a programmable systolic array (PDF)

Synthesizing optimal family of linear systolic arrays for matrix computations (PDF)

Theory for systolizing global computational problems (PDF)

New architectures for systolic hashing (PDF)

Linear systolic array for least-squares estimation (PDF)

A cellular algorithm for straight line extraction (PDF)

A one dimensional systolic array for solving arbitrarily large least mean square problems (PDF)

Performance evaluation of the HERMES multibit systolic array architecture for low level processing tasks (PDF)

On partitioning the Faddeev algorithm (PDF)

Systolic arrays for implementation of order-recursive least-squares adaptive filtering algorithms (PDF)

A systolic architecture for the symmetric tridiagonal eigenvalue problem (PDF)

Systolic FFT algorithms on Boolean cube networks (PDF)

Parallel architectures for artificial neural nets (PDF)

Stereo matching of satellite images with transputers (PDF)

The use of linear arrays for image processing (PDF)

A million transistor systolic array graphics engine (PDF)

A systolic array with constant I/O bandwidth for the generalized Fourier transform (PDF)

A massively parallel systolic array processor system (PDF)

Implementation of array structured maximum likelihood decoders (PDF)

Regular processor arrays for matrix algorithms with pivoting (PDF)

Systolic algorithms for some scheduling and graph problems (Abstract)

A shortperiodic two-dimensional systolic sorting algorithm (PDF)

A block algorithm for the algebraic path problem and its execution on a systolic array (PDF)

The design of a systolic array system for linear state equations (PDF)

Mapping strategy for automatic design of systolic arrays (PDF)

Transitive closure on an instruction systolic array (PDF)

The derivation of regular synchronous circuits (PDF)

Systolic arrays for group explicit methods for solving parabolic partial differential equations (PDF)

Formal derivation of systolic arrays-a case study (PDF)

Parallel algorithms and systolic array designs for RSA cryptosystem (PDF)

Mapping systolic algorithms into shuffle arrays (PDF)

A systolic algorithm and architecture for solving sets of linear equations with multi-band coefficient matrix (PDF)

Scheduling a system of affine recurrence equations onto a systolic array (PDF)

SYSTARS: A CAD tool for the synthesis and analysis of VLSI systolic/wavefront arrays (PDF)

Time optimal linear schedules for algorithms with uniform dependencies (PDF)

Broadcast removal in systolic algorithms (PDF)

HIFI: a functional design system for VLSI processing arrays (PDF)

A systematic approach to the design of modular systolic arrays (PDF)

A pragmatic approach to systolic design (PDF)

Uniformization of linear recurrence equations: a step toward the automatic synthesis of systolic arrays (PDF)

A linear algebraic model of algorithmic-based fault tolerance (PDF)

New conditions for testability of two-dimensional bilateral arrays (PDF)

On the design of easily testable and reconfigurable systolic arrays (PDF)

The ASP, a fault tolerant VLSI/ULSI/WSI associative string processor for cost-effective systolic processing (PDF)

A parallel video signal processor, based on overlap save techniques (PDF)

Cellular array processor CAP and applications (PDF)

A probabilistic model for clock skew (PDF)

Interconnection complexity study for a piggy back WSHP GaAs systolic processor (PDF)

Policies for fault-tolerance through mixed space- and time-redundancy in semi-systolic FFT arrays (PDF)

A systolic array for fault tolerant digital signal processing using a residue number system approach (PDF)

A systolic integrated circuit integer divider (PDF)

An efficient asynchronous multiplier (PDF)

Homogeneous multicomputer type DSP system NOVI for parallel signal processing (PDF)

A multiprocessor system utilizing enhanced DSPs for image processing (PDF)

Architecture of SIPS, a real time image processing system (PDF)

A reconfigurable VLSI array for reliability and yield enhancement (PDF)

A systolic square root information Kalman filter (PDF)

Bit-level systolic arrays for IIR filtering (PDF)

A high level synthesis tool for systolic designs (PDF)

Systolic array system for vector quantization using transformed sub-band coding (PDF)

A systematic approach to bit recursive systolic array design (PDF)

Systolic communication (PDF)