Proceedings 13th IEEE Sympsoium on Computer Arithmetic (PDF)
Forward (PDF)
Dedication (PDF)
Committees (PDF)
Reviewers (PDF)
A Radix-8 CMOS S/390 Multiplier (Abstract)
A GaAs 32-bit Adder (Abstract)
SRT Division Architectures and Implementations (Abstract)
On Radix Representation of Rings (Abstract)
Theory and applications for a double-base number system (Abstract)
On the Design of IEEE Compliant Floating Point Units (Abstract)
A Priori Worst-Case Error Bounds for Floating-Point Computations (Abstract)
Multiprecision Division on an 8-bit Processor (Abstract)
Design and implementation of an RNS division algorithm (PDF)
Exponentiation using Division Chains (Abstract)
Implementing Multiply-Accumulate Operation in Multiplication Time (Abstract)
CORDIC Vectoring with Arbitrary Target Value (Abstract)
Fast Rotations: Low-cost Arithmetic Methods for Orthonormal Rotation (Abstract)
Generating a Power of an Operand by a Table Look-up and a Multiplication (Abstract)
Towards Correctly Rounded Transcendentals (Abstract)
Pipelined Packet-Forwarding Floating Point: I. Foundations and a Rounder (Abstract)
Pipelined Packet-Forwarding Floating Point: II. An Adder (Abstract)
The SNAP Project: Design of Floating Point Arithmetic Units (Abstract)
Fast Table-Driven Algorithms for Interval Elementary Functions (Abstract)
Symmetric Bipartite Tables for Accurate Function Approximation (Abstract)
High-Performance Hardware for Function Generation (Abstract)
Arithmetic Co-transformations in the Real and Complex Logarithmic Number Systems (Abstract)
Real/Complex Reconfigurable Arithmetic Using Redundant Complex Number Systems (Abstract)
Algorithms for Multi-Exponentiation Based on Complex Arithmetic (Abstract)
Fraction-Free RNS Algorithms for Solving Linear Systems (Abstract)
Fast Software Exponentiation in GF(2^k) (Abstract)
An IWS Montgomery Modular Multiplication Algorithm (Abstract)
Scaled and Unscaled Residue Number System to Binary Conversion Techniques using the Core Function (Abstract)
On-the-Fly Algorithms and Sequential Machines (Abstract)
The Half-Adder Form and Early Branch Condition Resolution (Abstract)
Synchronous Up/Down Counter with Clock Period Independent of Counter Size (Abstract)
A Q-Coder Algorithm with Carry Free Addition (Abstract)
Author Index (PDF)