CSDL - 1987 IEEE 8th Symposium on Computer Arithmetic (ARITH) - Table of Contents

Computer Arithmetic, IEEE Symposium on (1987)

Como, Italy Italy

May 18, 1987 to May 21, 1987

ISBN: 0-8186-0774-2

TABLE OF CONTENTS

A design of time-optimum and register-number-minimum systolic convolver (PDF)

Hiroshi Umeo , Osaka Electro-Communication University Neyagawashi, Hatsucho, 18-8, 572, Japan

pp. 5-12

Synthesis of area-efficient VLSI architectures for vector and matrix multiplication (PDF)

S. G. Smith , University of Edinburgh, Department of Electrical Engineering, King's Buildings, Mayfield Rd., EH9 3JL, Scotland

P. B. Denyer , University of Edinburgh, Department of Electrical Engineering, King's Buildings, Mayfield Rd., EH9 3JL, Scotland

pp. 13-20

Implementation of the single modulus complex ALU (PDF)

Rom-Shen Kao , University of Florida, USA

Fred J. Taylor , University of Florida, USA

pp. 21-27

Vector computations on an orthogonal memory access multiprocessing system (PDF)

Isaac D. Scherson , Department of Electrical and Computer Engineering, University of California, Santa Barbara, 93106, USA

Yiming Ma , Department of Electrical and Computer Engineering, University of California, Santa Barbara, 93106, USA

pp. 28-37

Structured arithmetic tiling of integrated circuits (PDF)

Tony M. Carter , University of Utah, Department of Computer Science, 3190a Merrill Engineering Building, Salt Lake City, 84112, USA

pp. 41-48

Fast area-efficient VLSI adders (PDF)

Tackdon Han , Department of Electrical and Computer Engineering, University of Massachusetts, Amherst, 01003, USA

David A. Carlson , Department of Electrical and Computer Engineering, University of Massachusetts, Amherst, 01003, USA

pp. 49-56

Area-time efficient arithmetic elements for VLSI systems (PDF)

Ramautar Sharma , AT&T Bell Laboratories Murray Hill, New Jersey 07974, USA

pp. 57-62

Parallel multipliers based on horizontal compressors (PDF)

Luigi Ciminiera , Dipartimento di Automatica e Informatica, Politecnico di Torino, corso Duca degli Abruzzi, 24, 10129, Italy

pp. 63-69

Algorithm for high speed shared radix 4 division and radix 4 square-root (PDF)

Jan Fandrianto , Weitek Corporation, Sunnyvale, California 94086, USA

pp. 73-79

Design of high speed MOS multiplier and divider using redundant binary representation (PDF)

Shigeo Kuninobu , Semiconductor Research Center, Matsushita Electric Industrial Co. Ltd., Moriguchi, Osaka, 570 Japan

Tamotsu Nishiyama , Semiconductor Research Center, Matsushita Electric Industrial Co. Ltd., Moriguchi, Osaka, 570 Japan

Hisakazu Edamatsu , Semiconductor Research Center, Matsushita Electric Industrial Co. Ltd., Moriguchi, Osaka, 570 Japan

Takashi Taniguchi , Semiconductor Research Center, Matsushita Electric Industrial Co. Ltd., Moriguchi, Osaka, 570 Japan

Naofumi Takagi , Department of Information Science, Faculty of Engineering, Kyoto University, 606 Japan

pp. 80-86

Fast multiply and divide for a VLSI floating-point unit (PDF)

B. K. Bose , Department of Electrical Engineering and Computer Sciences, University of California, Berkeley, 94720, USA

L. Pei , Department of Electrical Engineering and Computer Sciences, University of California, Berkeley, 94720, USA

G. S. Taylor , Department of Electrical Engineering and Computer Sciences, University of California, Berkeley, 94720, USA

D. A. Patterson , Department of Electrical Engineering and Computer Sciences, University of California, Berkeley, 94720, USA

pp. 87-94

On the implementation of shifters, multipliers, and dividers in VLSI floating point units (PDF)

Victor Peng , Digital Equipment Corporation, 75 Reed Road, Hudson, MA01749, USA

Sridhar Samudrala , Digital Equipment Corporation, 75 Reed Road, Hudson, MA01749, USA

Moshe Gavrielov , Digital Equipment Corporation, 75 Reed Road, Hudson, MA01749, USA

pp. 95-102

The FELIN arithmetic coprocessor chip (PDF)

M. Cosnard , CNRS, Lab. TTM3, INPG, 46 Av. Félix-Viallet, 38031 Grenoble Cedex, FRANCE

A. Guyot , CNRS, Lab. TTM3, INPG, 46 Av. Félix-Viallet, 38031 Grenoble Cedex, FRANCE

B. Hochet , CNRS, Lab. TTM3, INPG, 46 Av. Félix-Viallet, 38031 Grenoble Cedex, FRANCE

J.-M. Muller , CNRS, Lab. TTM3, INPG, 46 Av. Félix-Viallet, 38031 Grenoble Cedex, FRANCE

H. Ouaouicha , CNRS, Lab. TTM3, INPG, 46 Av. Félix-Viallet, 38031 Grenoble Cedex, FRANCE

P. Paul , CNRS, Lab. TTM3, INPG, 46 Av. Félix-Viallet, 38031 Grenoble Cedex, FRANCE

E. Zysman , CNRS, Lab. TTM3, INPG, 46 Av. Félix-Viallet, 38031 Grenoble Cedex, FRANCE

pp. 107-112

CORDIC arithmetic for an SVD processor (PDF)

Joseph R. Cavallaro , School of Electrical Engineering, Cornell University-Ithaca, New York 14853, USA

Franklin T. Luk , School of Electrical Engineering, Cornell University-Ithaca, New York 14853, USA

pp. 113-120

Evaluating elementary functions with Chebyshev polynomials on pipeline nets (PDF)

Kai Hwang , Department of Electrical Engineering-Systems, University of Southern California, Los Angeles, 90089, U.S.A.

H.C. Wang , Department of Electrical Engineering-Systems, University of Southern California, Los Angeles, 90089, U.S.A.

Z. Xu , Department of Electrical Engineering-Systems, University of Southern California, Los Angeles, 90089, U.S.A.

pp. 121-128

Toward an ideal computer arithmetic (PDF)

T.E. Hull , Department of Computer Science, University of Toronto, Canada M5S 1A4

M.S. Cohen , Department of Computer Science, University of Toronto, Canada M5S 1A4

pp. 131-138

A closed computer arithmetic (PDF)

F. W. J. Olver , Institute for Physical Science and Technology, University of Maryland, College Park, 20742, U.S.A.

pp. 139-143

Implementation of level-index arithmetic using partial table look-up (PDF)

F. W. J. Olver , IPST, University of Maryland, College Park, 20742, U.S.A.

P. R. Turner , IPST, University of Maryland, College Park, 20742, U.S.A.

pp. 144-147

On error analysis in arithmetic with varying relative precision (PDF)

James W. Demmel , Courant Institute, 251 Mercer Str., New York, 10012, USA

pp. 148-152

A new real number representation and its operation (PDF)

Hozumi Hamada , Central Research Laboratory, Hitachi Ltd., Kokubunji, Tokyo 185, Japan

pp. 153-157

Systolic solution of linear systems over GF(p) with partial pivoting (PDF)

Bertrand Hochet , CNRS, Laboratoire TIM3, BP 68, 38402 St Martin d'Hères Cedex, France

Patrice Quinton , CNRS, IRISA, 35042 Rennes Cedex, France

Yves Robert , CNRS, LaboratoireTIM3 and IBM ECSEC, Via Giorgione 159, 00147 Roma, Italy

pp. 161-168

Systolic & semi-systolic digit serial multipliers (PDF)

Poras T. Balsara , Department of Computer Science, Pennsylvania State University, University Park, 16802, USA

Robert M. Owens , Department of Computer Science, Pennsylvania State University, University Park, 16802, USA

pp. 169-173

Systolic up/down counters with zero and sign detection (PDF)

Behrooz Parhami , Computer Science Department, University of Waterloo, Canada

pp. 174-178

A radix-4 on-line division algorithm (PDF)

Pad K.-G. Tu , Computer Science Department, University of California, Los Angeles, 90024, USA

Milos D. Ercegovac , Computer Science Department, University of California, Los Angeles, 90024, USA

pp. 181-187

A novel floating-point online division algorithm (PDF)

Haixiang Lin , Delft University of Technology, The Netherlands

Henk J. Sips , Delft University of Technology, The Netherlands

pp. 188-195

On-line scheme for computing rotation factors (PDF)

Milos D. Ercegovac , UCLA Computer Science Department, University of California, Los Angeles, 90024, USA

Tomas Lang , UCLA Computer Science Department, University of California, Los Angeles, 90024, USA

pp. 196-203

A bit-serial arithmetic unit for rational arithmetic (PDF)

Peter Kornerup , Aarhus University, Denmark

David W. Matula , Southern Methodist University, Dallas, Texas, USA

pp. 204-211

A normalization algorithm for truncated p-adic arithmetic (PDF)

A. Colagrossi , ISTITUTO SUPERIORE DI SANITA' - Viale Regina Elena 299, 00161 Roma, Italy

A. Miola , DIPARTIMENTO DI INFORMATICA E SISTEMISTICA UNIVERSITA' DI ROMA “LA SAPIENZA”, Via Buonarroti 12, 00185, Italy

pp. 212-216

Protecting convolution-type aritmetic array calculations with generalized cyclic codes (PDF)

G. Robert Redinbo , Department of Electrical and Computer Engineering, University of California, Davis, 95616 USA

pp. 219-225

Error detection and correction for addition and subtraction, through use of higher radix extensions of hamming codes (PDF)

James E. Robertson , Department of Computer Science, University of Illinois at Urbana-Champaign, 61801, USA

pp. 226-229

Fault-tolerant systolic arrays: An approach based upon residue arithmetic (PDF)

Vincenzo Piuri , Department of Electronics, Politecnico di MiLano, Piazza L. da Vinci 32, 120133, Italy

pp. 230-238

A formal approach to rounding (PDF)

Geoff Barrett , Oxford University Programming Research Group, USA

pp. 247-254

The development of a floating-point validation package (PDF)

J. Du Croz

M. Pont

pp. 255

Arithmetic for vector processors (PDF)

R. Kirchner , Fachbereich Informatik, Universität Kaiserlautern, Fakultät für Mathematik, Universität Karlsruhe, West Germany

U. Kulisch , Fachbereich Informatik, Universität Kaiserlautern, Fakultät für Mathematik, Universität Karlsruhe, West Germany

pp. 256-269

Computer arithmetic and ill-conditioned algebraic problems (PDF)

Gunter Schumacher , Universität Karlsruhe, Institut für Angewandte Mathematik, Kaiserstr. 12, D-7500, West-Germany

pp. 270-276