The design of two easily-testable VLSI array multipliers (PDF)

A comparison of ALU structures for VLSI technology (PDF)

On design and performance of VLSI based parallel multiplier (PDF)

On fast binary addition in MDS Technologies (PDF)

Sign detection in Non-Redundant Residue Number System with reduced information (PDF)

Representation and processing of fractions in a residue system (PDF)

Systems of numeration (PDF)

A multiplier with multiple error correction capability (PDF)

Some schemes for fast serial input multipliers (PDF)

Fast iterative multiplying array (PDF)

Experience with a high level language that supports interval arithmetic (PDF)

ADA floating-point arithmetic as a basis for portable numerical software (PDF)

On the numerical algorithms formulated in computer arithmetic (PDF)

A numeric error algebra (PDF)

A higher-radix division with simple selection of quotient digits (PDF)

Square-root algorithms for high-speed digital circuits (PDF)

Some tricks of the (floating point) trade (PDF)

On bit sequential multipliers (PDF)

Arithmetic on the ELXSI System 6400 (PDF)

Matrix multiplication on LUCAS (PDF)

Multi-operand associative arithmetic (PDF)

An IEEE floating point arithmetic implementation (PDF)

Fast matrix solver in GF(2) (PDF)

Vector reduction methods for arithmetic pipelines (PDF)

On-line multiplicative normalization (PDF)

Numerical limitations on the design of digit online networks (PDF)

Arithmetic for a high-speed adaptive learning network element (PDF)

Applications for arithmetic error codes in large, high-performance computers (PDF)

Models for VLSI implementation of residue number system arithmetic modules (PDF)

Continued fractions for high-speed and high-accuracy computer arithmetic (PDF)

Floating-point recurring rational arithmetic system (PDF)

An order preserving finite binary encoding of the rationals (PDF)

A unified view of approximate rational arithmetic and rational interpolation (PDF)