Field-Programmable Custom Computing Machines, Annual IEEE Symposium on
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Abstract

Improvements in the FPGA technology have resulted in introduction of reconfigurable computing machines, where the hardware adapts itself to the running application to gain speedup. This paper presents a top-down compilation method, under development, for such systems. We compile a C program into hierarchical VHDL source files, and annotate them with the placement information of the hardware modules to be configured on the FPGA. Static scheduling combined with a fast, two-stage placement core reduces the compilation time of large programs to minutes.
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