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IEEE Micro
Volume 23, Issue 6
Nov.-Dec. 2003
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Table of Contents
Columns and Departments
Letters
Freely available from IEEE.
pp. 5
Columns and Departments
Where we're going
Full-text access may be available. Sign in or learn about subscription options.
pp. 6-7
by
Richard Mateosian
Features
Guest Editors' Introduction: Micro's Top Picks from Microarchitecture Conferences
Freely available from IEEE.
pp. 8-10
by
Charles Moore
,
Kevin W. Rudd
,
Ruby B. Lee
,
Pradip Bose
Features
Checkpoint Processing and Recovery: An Efficient, Scalable Alternative to Reorder Buffers
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pp. 11-19
by
Haitham Akkary
,
Ravi Rajwar
,
Srikanth T. Srinivasan
Features
Runahead Execution: An Effective Alternative to Large Instruction Windows
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pp. 20-25
by
Onur Mutlu
,
Jared Stark
,
Chris Wilkerson
,
Yale N. Patt
Features
The Jrpm System for Dynamically Parallelizing Sequential Java Programs
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pp. 26-35
by
Michael K. Chen
,
Kunle Olukotun
Features
Scalable Vector Processors for Embedded Systems
Full-text access may be available. Sign in or learn about subscription options.
pp. 36-45
by
Christoforos E. Kozyrakis
,
David A. Patterson
Features
Exploiting ILP, TLP, and DLP with the Polymorphous TRIPS Architecture
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pp. 46-51
by
Karthikeyan Sankaralingam
,
Ramadass Nagarajan
,
Haiming Liu
,
Changkyu Kim
,
Jaehyuk Huh
,
Doug Burger
,
Stephen W. Keckler
,
Charles Moore
Features
Temperature-Aware Computer Systems: Opportunities and Challenges
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pp. 52-61
by
Kevin Skadron
,
Mircea R. Stan
,
Wei Huang
,
Sivakumar Velusamy
,
Karthik Sankaranarayanan
,
David Tarjan
Features
Dynamic Frequency and Voltage Scaling for a Multiple-Clock-Domain Microprocessor
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pp. 62-68
by
Grigorios Magklis
,
Greg Semeraro
,
David H. Albonesi
,
Steven G. Dropsho
,
Sandhya Dwarkadas
,
Michael L. Scott
Features
Measuring Architectural Vulnerability Factors
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pp. 70-75
by
Shubhendu S. Mukherjee
,
Christopher T. Weaver
,
Joel Emer
,
Steven K. Reinhardt
,
Todd Austin
Features
Transient-Fault Recovery for Chip Multiprocessors
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pp. 76-83
by
Mohamed A. Gomaa
,
Chad Scarbrough
,
T. N. Vijaykumar
,
Irith Pomeranz
Features
Discovering and Exploiting Program Phases
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pp. 84-93
by
Timothy Sherwood
,
Erez Perelman
,
Greg Hamerly
,
Suleyman Sair
,
Brad Calder
Features
Addressing Workload Variability in Architectural Simulations
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pp. 94-98
by
Alaa R. Alameldeen
,
David A. Wood
Features
Nonuniform Cache Architectures for Wire-Delay Dominated On-Chip Caches
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pp. 99-107
by
Changkyu Kim
,
Doug Burger
,
Stephen W. Keckler
Features
Token Coherence: A New Framework for Shared-Memory Multiprocessors
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pp. 108-116
by
Milo M.K. Martin
,
Mark D. Hill
,
David A. Wood
Features
Transactional Execution: Toward Reliable, High-Performance Multithreading
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pp. 117-125
by
Ravi Rajwar
,
James Goodman
Features
Speculative Synchronization: Programmability and Performance for Parallel Codes
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pp. 126-134
by
Jos? F. Mart?nez
,
Josep Torrellas
Annual Index
2003 IEEE Micro Annual Index, Vol. 23
Freely available from IEEE.
pp. 136-144
Showing 19 out of 19
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