http://www.computer.org/micro IEEE Micro, a bimonthly publication of the IEEE Computer Society, reaches an international audience of microcomputer and microprocessor designers, system integrators, and users. Readers want to increase their technical knowledge of computers and peripherals; systems, components, and subassemblies; communications, instrumentation, and control equipment; and software. en-us Sat, 18 May 2013 10:00:06 GMT http://csdl.computer.org/common/images/logos/micro.gif List of recently published journal articles http://www.computer.org/micro http://doi.ieeecomputersociety.org/10.1109/MM.2013.29 Modern memory controllers employ sophisticated address mapping, command scheduling, and power management optimizations to alleviate the adverse effects of DRAM timing and resource constraints on system performance. A promising way of improving the versatility and efficiency of these controllers is to make them programmable. Unfortunately, the stringent latency and throughput requirements of modern DDRx devices have rendered such programmability largely impractical, confining DDRx controllers to fixed-function hardware. PARDIS is the first programmable memory controller that can meet these challenges, and satisfy the performance requirements of a high-speed DDRx interface. http://doi.ieeecomputersociety.org/10.1109/MM.2013.29 http://doi.ieeecomputersociety.org/10.1109/MM.2013.52 Microprocessor voltage levels traditionally include substantial margin to ensure reliable operation despite variations in manufacturing, workload, and environmental parameters. This margin allows the microprocessor to function correctly during worst-case conditions, but during typical operation it is larger than necessary and wastes energy. We present a mechanism that reduces excess voltage margin by (1) introducing a critical path monitor (CPM) circuit that measures available timing margin in real-time, (2) coupling the CPM output to the clock generation circuit to rapidly adjust clock frequency in response to excess or inadequate timing margin, and (3) adjusting the processor voltage level periodically in firmware to achieve a specified average clock frequency target. We first demonstrated this mechanism in an IBM POWER7 server and proved its effectiveness in the POWER7+ product. Power consumption on the Vdd rail reduced by 11% for SPEC CPU2006 workloads with negligible performance loss yet increased protection against noise events. http://doi.ieeecomputersociety.org/10.1109/MM.2013.52 http://doi.ieeecomputersociety.org/10.1109/MM.2013.51 Conventional chips are designed to sustain near-peak performance levels indefinitely. However, the tight thermal constraints of mobile devices, which limit sustainable performance, and the bursty nature of interactive mobile applications call for a new design focus: enhancing end-user responsiveness rather than sustained throughput. To that end, this article explores computational sprinting, wherein a mobile device temporarily exceeds sustainable thermal limits to provide a brief, intense burst of computation in response to user input. By enabling ten-fold more computation within the timescale of human patience, sprinting has the potential to fundamentally change the user experience that an interactive application can provide. http://doi.ieeecomputersociety.org/10.1109/MM.2013.51 http://doi.ieeecomputersociety.org/10.1109/MM.2013.50 Recent efforts to standardize concurrency semantics for languages and processor ISA assumes that a memory access is data-race-free (``safe'') unless annotated by the programmer. Compiler and hardware is expected to preserve SC semantics only for the annotated (``unsafe'') accesses. Instead, we argue for a safety-first approach, where we assume that a memory access is unsafe unless it is proven to be safe either through compiler static analysis or runtime analysis. We show that the performance or even the design cost of preserving SC for unsafe accesses is insignificant in practice. Our hardware preserves SC by employing an unordered store buffer for fast-tracking safe stores and allowing later memory accesses to proceed without a memory ordering related stall. Together with an efficient SC-preserving compiler, it helps us guarantee SC semantics at the language-level for all programs for a low cost. http://doi.ieeecomputersociety.org/10.1109/MM.2013.50 http://doi.ieeecomputersociety.org/10.1109/MM.2013.27 The ability to safely keep a secret in memory is central to the vast majority of security schemes, but storing and erasing these secrets is a difficult problem in the face of an attacker who can obtain unrestricted physical access to the underlying hardware. Depending on the memory technology, the very act of storing a 1 instead of a 0 can have physical side effects measurable even after the power has been cut. Just as we use architectural techniques to detect and correct errors, so too we can create efficient methods to hide critical bits from physical inspection. We present a first step towards this goal by focusing on one of the backbones of any hardware system: on-chip memory. We examine the relationship between security, area, and efficiency in these architectures, and quantitatively examine the resulting systems through cryptographic analysis and microarchitectural impact. In the end, we are able to find an efficient scheme in which, even if an adversary is able to inspect the value of a stored bit with a probabilistic error of only 5%, our system will be able to prevent that adversary from learning any information about the original un-coded bits with 99.9999999999% probability. http://doi.ieeecomputersociety.org/10.1109/MM.2013.27 http://doi.ieeecomputersociety.org/10.1109/MM.2013.23 User inputs tend to change the execution characteristics of applications; their interactions with cache, network, storage and other systems tend to be data-dependent. There have been many attacks that exploit the observable side- effects of these execution characteristics to expose secret information. In response, researchers have proposed countermeasures to protect against these attacks. However there is currently no systematic, holistic methodology for understanding information leakage. As a result, it is not well known how design decisions affect information leakage or the vulnerability of systems to side-channel attacks. In this paper, we propose a metric for measuring information leakage called Side-channel Vulnerability Factor (SVF). SVF is based on our observation that all side-channel attacks -- ranging from physical to microarchitectural to software -- rely on recognizing leaked execution patterns. SVF quantifies patterns in attackers' observations and measures their correlation to the victim's actual execution patterns and in doing so captures systems' predisposition to leak information. In a detailed case study of on-chip memory systems, SVF measurements help expose unexpected vulnerabilities in whole-system designs and shows how designers can make performance-security trade-offs. Thus, SVF provides a quantitative approach to securing computer architecture. http://doi.ieeecomputersociety.org/10.1109/MM.2013.23 http://doi.ieeecomputersociety.org/10.1109/MM.2013.22 Medfield is the code name for the first Intel® smartphone platform that delivers an Intel® Architecture (IA) processor into a handheld form factor. Medfield is built around the Intel® Atom™ Z2480 Processor [1, 2]. The platform uses the Intel® Hi-K 32nm process technology [3] to deliver compelling end-user experience within the low power constraints demanded by the form factor [4, 5]. In this article, we will cover platform and system-on-a-chip (SoC) design constraints ranging from board layout, chip packaging, silicon design to software architecture. We put a special emphasis on the hardware and software power management techniques that allowed the product to meet smartphone compatible battery life targets. http://doi.ieeecomputersociety.org/10.1109/MM.2013.22 http://doi.ieeecomputersociety.org/10.1109/MM.2013.7 Memory access rate is a primary performance bottleneck in high-performance networking systems. The MoSys Bandwidth Engine® family of ICs provides a significant improvement in effective memory performance by using high-speed serial I/O’s, many banks of memory, a low-latency, highly efficient protocol, and intelligence within the device. The first member of the family can perform 2 billion 72-bit reads per second or 1 billion read-modify-write operations per second. http://doi.ieeecomputersociety.org/10.1109/MM.2013.7 http://www.computer.org/portal/site/micro/ IEEE Micro http://www.computer.org/portal/site/micro/