http://www.computer.org/micro IEEE Micro, a bimonthly publication of the IEEE Computer Society, reaches an international audience of microcomputer and microprocessor designers, system integrators, and users. Readers want to increase their technical knowledge of computers and peripherals; systems, components, and subassemblies; communications, instrumentation, and control equipment; and software. en-us Wed, 4 Jan 2012 11:00:01 GMT http://csdl.computer.org/common/images/logos/micro.gif List of recently published journal articles http://www.computer.org/micro http://doi.ieeecomputersociety.org/10.1109/MM.2011.108 Blue Gene/Q™ represents the third generation in the IBM Blue Gene® line of supercomputer systems. Installations will be able to scale to a performance of tens of PetaFLOP/s. Blue Gene/Q follows the same philosophy as the earlier Blue Gene/L and Blue Gene/P systems, namely to build a massively parallel high performance computing (HPC) system out of very power-efficient processor chips. Such power-efficient chips, in turn, allow very dense packaging, which consequently will result in power efficient, cost efficient and floor-space efficient systems. A focus on reliability during all phases of the design also contributes to the feasibility of scaling to large systems, and will lower the total cost of ownership. The heart of a Blue Gene/Q system is the Compute chip, which combines processors, memory and communications functions on a single chip. This paper will discuss the Blue Gene/Q Compute chip architecture and design. http://doi.ieeecomputersociety.org/10.1109/MM.2011.108 http://opac.ieeecomputersociety.org/opac?year=2011&volume=31&issue=06&acronym=micro IEEE Micro http://www.computer.org/portal/site/micro/ http://doi.ieeecomputersociety.org/10.1109/MM.2011.96 This paper describes the IBM Blue Gene/Q interconnection network and message unit. Blue Gene/Q is the third generation in the IBM Blue Gene line of massively parallel supercomputers and can be scaled to 20 PF/s and beyond. The network and the highly parallel message unit, which provides the functionality of a network interface, are integrated onto the same chip as the processors and cache memory, and consume 8% of the area. For better application scalability and performance, we describe new routing algorithms and techniques to parallelize the injection and reception of packets in the network interface. We measure and present hardware performance results. http://doi.ieeecomputersociety.org/10.1109/MM.2011.96 http://doi.ieeecomputersociety.org/10.1109/MM.2011.98 The Tofu interconnect was developed by Fujitsu as a national project of MEXT. The goal of the project is to develop one of the world’s most powerful general purpose supercomputer systems and grand challenge applications, and to build a core research hub for computational science. The Tofu interconnect provides the scalability to implement the 10 petaFLOPS ‘K computer’ system which has more than 80,000 nodes. The network topology is a 6D mesh/torus. Quad network interfaces provide high throughput. The barrier interface is dedicated to offloading collective communications. This paper describes the Tofu interconnect architecture, the Tofu network router, the Tofu network interface, and the Tofu barrier interface, and also presents preliminary evaluation results. http://doi.ieeecomputersociety.org/10.1109/MM.2011.98 http://doi.ieeecomputersociety.org/10.1109/MM.2011.97 TianHe-1A, a large scale supercomputer features hybrid multi-core CPU and GPU computing, utilizes a proprietary high-bandwidth, low-latency interconnect fabric to achieve the optimized balance of computation and communication capabilities. This paper describes the interconnect design in TianHe-1A, including the network routing and network interface chip. Based on the scalable user-level communication and offloaded collective operations, our message passing service has achieved 6340MB/s unidirectional bandwidth and low latency collective operations at large scale. http://doi.ieeecomputersociety.org/10.1109/MM.2011.97 http://doi.ieeecomputersociety.org/10.1109/MM.2011.81 This paper presents a new approach for wireless communications: software-defined radio (SDR) employing cloud computing concepts. SDR describes radio transmitters and receivers that implement the digital signal processing in software running on general-purpose hardware. SDR clouds are data centers that connect to distributed antennas via high-speed communication links. The analog signal processing is accomplished at the antenna sites, whereas the sampled data are processed in the data center. This is possible thanks to the advances in optical networking technology. SDR clouds provide a scalable solution for the evolution of wireless communications. This paper focuses on the resource management implications. It proposes a hierarchical approach for dynamically managing the real-time computing constraints of wireless communications systems running on the SDR cloud. http://doi.ieeecomputersociety.org/10.1109/MM.2011.81 http://doi.ieeecomputersociety.org/10.1109/MM.2011.80 This article describes the design of an individual-based simulation engine which aims to use modern general purpose multicore and multiprocessor computers to their fullest potential. It is dedicated to interactive simulations of highly dynamic multiagent systems where entities can move, change, appear, disappear and interact with each other and the user at any time. After studying some of the common memory access issues associated with this kind of computer, we list the main choices considered for the design of our engine. Experiments with various computers, operating systems and compilers yield very satisfying results in terms of performance and scalability relating to the number of cores used. http://doi.ieeecomputersociety.org/10.1109/MM.2011.80