IEEE Design and Test of Computers

Not just research as usual

This issue of IEEE Design & Test focuses on one of the five centers within the Focus Center Research Program (FCRP), the Gigascale Systems Research Center, which addresses systems architecture and design aspects of electronics systems in the late- and post-silicon eras. Six articles written by the center researchers provide an overview of the visions and their key research results. This special issue also features a dynamic interview with Intel Chair Craig Barrett, who is generally considered to be the "father" of the FCRP. Finally, there is a general-interest article that reviews several chip-cooling techniques and presents an alternative approach based on a digital-microfluidic platform.

Guest Editors' Introduction: System IC Design Challenges beyond 32 nm

This special issue highlights ongoing research to address some of the challenges in the design of large ICs with dimensions well below 100 nm. The Gigascale Systems Research Center is organized around four themes and a design driver, and each is represented in this issue. There is also an exciting interview with Intel chair Craig Barrett. Accompanying the theme articles are three sidebars written by industry leaders (Richard Oehler of AMD, Ajith Amerasekera of Texas Instruments, and Leon Stok of IBM) on the challenges they see on the horizon, the paths being taken to address these challenges, and the role university programs can play. In addition, a Perspectives article by John Zolper discusses the value of this collaborative program to US national interests, including national security. Finally, there is a Last Byte column by the FCRP executive director Betsy Weitzman.

Challenges and Solutions for Late- and Post-Silicon Design

The ability to stay on pace with Moore's law has been critical in providing for exponentially increasing computation capabilities per unit cost, and thus regularly enabling new applications. Maintaining this pace has always been challenging, but the challenges loom even larger as we approach the physical and economic limits of technology scaling. The resulting stress already is causing many companies to move toward fabless and fablight business models, with increased emphasis on system-level design technology. Another observable trend is the decline of ASICs and the corresponding growth in programmable platforms. These changes challenge traditional design technologies such as test and verification, and their interaction with emerging issues related to variability, reliability, and migration to post-silicon devices. This article proposes a roadmap of potential solutions for the future, based on managing massive concurrency, increasing self-adaptivity and resiliency, and adopting new computation models.

Interview: A Discussion with Intel Chair Craig Barrett

This is an in-depth interview with Craig Barrett. In addition to being the chair of Intel, Barrett is one of the fathers of the Focus Center Research Program, and he chairs its governing council. In this wide-ranging interview, he discusses the industry challenges on the horizon, the role universities can play in addressing these challenges, the state and future of American education, and the value-and necessity-of collaborative programs. Attendees included EIC Tim Cheng (University of California, Santa Barbara), Guest Editors William Joyner and David Yeh (Semiconductor Research Corp.), and Gigascale Systems Research Center Director Jan Rabaey (University of California, Berkeley).

The Concurrency Challenge

Commercial microprocessors are converging on multiprocessor architectures with multiple cores on a single die. Unless software adapts and utilizes these parallel systems, the fundamental value proposition behind the semiconductor and computer industries will falter. According to the authors of this article, successful programming environments for these processors must be application centric and protect application programmers from as many hardware idiosyncrasies as possible. In particular, they envision a methodology in which application developers write code by inserting specific modules, constraints, and error handlers into application frameworks to derive working code. Ideally, most of these programmers should not need to know that they are generating concurrent programs. Solutions should be derived according to engineering and architectural principles that can be replicated and applied across a wide range of applications. Robust strategies to help developers debug the functionality and performance of their code without seeing the complexity of concurrent execution will be critical to the success of this methodology.

The GSRC: Bridging Academia and Industry

Finding parallelism in application code and exploiting it through automatic tools is the Holy Grail of high-performance computing. Success in this endeavor requires major industry participation, not only among processor chip and hardware system developers but also among operating system and tool providers. Most important, participation is needed among the application writers and developers who will in many ways drive toward acceptable solutions.

Reliable Systems on Unreliable Fabrics

The continued scaling of silicon fabrication technology has led to significant reliability concerns, which are quickly becoming a dominant design challenge. Design integrity is threatened by complexity challenges in the form of immense designs defying complete verification, and physical challenges such as silicon aging and soft errors, which impair correct system operation. The Gigascale Systems Research Center Resilient-System Design Team is addressing these key challenges through synergistic research thrusts, ranging from near-term reliability stress reduction techniques to methods for improving the quality of today's silicon, to longer-term technologies that can detect, recover, and repair faulty systems. These efforts are supported and complemented by an active fault-modeling research effort and a strong focus on functional-verification methodologies. The team's goal is to provide highly effective, low-cost solutions to ensure both correctness and reliability in future designs and technology nodes, thereby extending the lifetime of silicon fabrication technologies beyond what can be currently foreseen as profitable.

The Changing Design Landscape

This sidebar explains that the burden of enabling Moore's law to continue is gradually moving from the process technologists to the designers. As technology moves from 65 nm to 22 nm, the number of transistors on a big chip will go from approximately 2 billion to 15 billion. Technology scaling and the manufacturing process come with higher variations in transistors both locally and globally on a chip. Moreover, the large number of components on a single chip will lead to reliability, aging, and defect limitations that could no longer be eliminated through margins or overdesign. They must be detected and compensated without affecting the performance goals of the chip. The research direction of the GSRC is aimed at solutions to these obstacles, for the continued advancement of system performance needs.

The Search for Alternative Computational Paradigms

Nanometer processes are characterized by extremes of process variations, noise, soft errors, and other nonidealities, which threaten to nullify the intrinsic benefits of scaling. The resulting robustness and energy efficiency problem cannot be addressed in a cost-effective manner solely through advances in manufacturing. Alternative models of computation are needed that thrive in the presence of statistical variations in the underlying device and circuit fabric. This article explores communications-inspired models of computation supported by innovative robust circuit and logic fabric design approaches. These models share the common feature of leveraging dense networks with information exchange and coupling among nodes to enhance robustness without compromising energy efficiency. Promising post-silicon devices such as carbon nanotubes (CNTs) offer an attractive platform on which to build such computational systems. This article identifies opportunities and challenges in designing robust and low-power SoCs in emerging nanoscale process technologies, employing radically new modes of computation.

Variability and New Design Paradigms

In the late- and post-silicon eras, variation of all nanometer processes will continue to increase significantly. The industry is gradually addressing this situation and exposing more variability information to the designer. According to the Gigascale Systems Research Center, the deterministic era will be over for most on-chip applications and alternatives must be found. The author of this sidebar looks forward to the time when the two will meet: when more revolutionary design techniques will find their way into practical designs, and when one of the computational paradigms will suddenly be needed to cope with an unexpected surge in variability or reliability in a particular design or technology.

Is a Unified Methodology for System-Level Design Possible?

This article describes the principles of the design of embedded electronic systems from the perspective of the entire system. By not restricting this perspective to the electrical domain, a more disciplined, unified methodology can lead to more efficient system-level design. In a world where myriad wirelessly interconnected appliances are going to impact our everyday lives and where technology advances are posing fundamental problems at the nanodevice level, the most important challenge will be ensuring safe, secure, and effective design. A unified methodology is an essential ingredient for a successful use of technology in society.

Workloads of the Future

IT has transformed itself many times over the past decade. Yet a far more fundamental overhaul is in the making: the long-predicted world of fully ubiquitous computation and communication is finally emerging. Addressing the associated challenges and opportunities may require a fundamental rethinking of the way we do design. Most notably, the semiconductor industry must abandon its traditional component-oriented perspective and adopt a system vision. To meaningfully guide this process and fully exploit the offered opportunities, an understanding of what the workloads of the future may look like is necessary. This task is possible only through a joint effort of the application and design communities. This article characterizes the essential features of what the authors consider the dominant application classes of the future. It becomes apparent that these workloads operate under different quality metrics. Instead of performance or energy per function, metrics such as system latency, useful functionality per energy spent, and reliability and liability take center stage. The authors, therefore, issue a call to action for the creation of relevant benchmark libraries, each accompanied with a clear definition of the metrics relevant to their evaluation.

The GSRC's Role in Meeting Tomorrow's Design Challenges

In the late 1990s, the US Office of the Secretary of Defense (OSD) established a joint research program with the Semiconductor Industry Association (SIA) through the Semiconductor Research Corp. (SRC), known as the Focus Center Research Program. One of these FCRP centers is the Gigascale Systems Research Center (GSRC), whose focus is on the systems architecture and design aspects of electronics technology. The research of the GSRC is of great value to the US Department of Defense, since design remains an important challenge for DoD systems. This partnership is an excellent example of government and industry collaboration on precompetitive research of common interest and benefit.

A Digital-Microfluidic Approach to Chip Cooling

Thermal management has emerged as an increasingly important aspect of IC design. Elevated die temperatures are detrimental to circuit performance and reliability. Furthermore, hot spots due to spatially nonuniform heat flux in ICs can cause physical stress that further reduces reliability. The authors of this article review various chip-cooling techniques that have been proposed in the literature. They then present an alternative approach based on a recently invented digital-microfluidic platform that enables an adaptive cooling technique. This novel digital-fluid-handling platform uses a phenomenon known as electrowetting so that a vast array of discrete droplets of liquid, ranging from microliters to nanoliters and potentially to picoliters, can be independently moved along a substrate. Although this technology was originally developed for a biological and chemical lab on a chip, the authors show how it can be adapted for use as a fully reconfigurable, adaptive cooling platform.

With pick and shovel through our data

This is a review of Data Mining: Concepts, Models, Methods, and Algorithms (by Mehmed Kantardzic). Data mining is used to learn the characteristics of a population on the basis of a set of samples. One application of this in fabs is statistical postprocessing. As chips get bigger, test data volumes grow as well. It might be possible to mine this data to discover more about these chips and the processes to build them. This book is written at the right level for test engineers, and it doesn't include overly complex mathematical treatments of the concepts. Those in test can glean some good ideas here on how to apply data mining to get the most from their piles of test data, and on some of the tools that could help them.

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This newsletter provides news, events, and information related to the IEEE Computer Society's Design Automation Technical Committee and the EDA community.

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This newsletter covers news, research, and events related to the IEEE Council on Electronic Design Automation.

TTTC Newsletter

This newsletter provides information on past and upcoming events related to the IEEE Computer Society's Test Technology Technical Council and the test community.

Who knew this "experiment" would be so successful?

Focus Center Research Program executive director Betsy Weitzman looks back at the genesis of the FCRP, and looks forward to more groundbreaking research through multiuniversity collaboration and an industry-government-academia partnership.