http://www.computer.org/dt IEEE Design & Test of Computers offers original works describing the methods used to design and test electronic product hardware and supportive software. The magazine focuses on current and near-future practice, and includes tutorials, how-to articles, and real-world case studies. Topics include IC/module design, low-power design, electronic design automation, design/test verification, practical technology, and standards. IEEE Design & Test of Computers is published by the IEEE Computer Society in technical cosponsorship with the IEEE Circuits and Systems Society. en-us Wed, 4 Jan 2012 11:00:01 GMT http://csdl.computer.org/common/images/logos/dt.gif List of recently published journal articles http://www.computer.org/dt http://opac.ieeecomputersociety.org/opac?year=2011&volume=28&issue=06&acronym=dt IEEE Design and Test of Computers http://www.computer.org/portal/site/dt/ http://doi.ieeecomputersociety.org/10.1109/MDT.2011.75 The increasing complexity of integrated circuits pushes for more aggressive design optimizations, such as resetting only part of design registers, that can leave some registers in nondeterministic (X) states. Such Xs may invalidate the correctness of logic simulation due to X-optimism and X-pessimism, producing simulation waveforms that can not be trusted. Although formal methods can resolve the nondeterminism problem, they are not scalable enough to handle today's multi-million gate designs. To address this problem, we developed a scalable X-analysis methodology and successfully applied it to solve three real industrial problems --- one identifies missing Xs in RTL designs while the other two remove incorrect Xs to repair gate-level simulation. http://doi.ieeecomputersociety.org/10.1109/MDT.2011.75 http://doi.ieeecomputersociety.org/10.1109/MDT.2011.73 Speed-path debug is a critical step in improving clock frequency of a design to meet the performance requirement. However, speed-path debug based on functional patterns can be very expensive. In this paper, we explore speed-path debug techniques based on at-speed scan test patterns. Enhancements are implemented to improve over an earlier proposed scan-based speed-path diagnosis algorithm. We further report the application results by applying the improved algorithm to a leading-edge high-performance microprocessor design. http://doi.ieeecomputersociety.org/10.1109/MDT.2011.73 http://doi.ieeecomputersociety.org/10.1109/MDT.2011.72 Although communication fabrics at the microarchitectural level are mainly composed of standard primitives such as queues and arbiters, to get an executable model one has to connect these primitives with glue logic to complete the description. In this paper we identify a richer set of microarchitectural primitives that allows us to describe complete systems by composition alone. This enables us to build models faster (since models are now simply wiring diagrams at an appropriate level of abstraction) and to avoid common modeling errors such as inadvertent loss of data due to incorrect timing assumptions. Our models are formal and they are used for model checking as well as dynamic validation and performance modeling. However, unlike other formalisms this approach leads to a precise yet intuitive graphical notation for microarchitecture that captures timing and functionality in sufficient detail to be useful for reasoning about correctness and for communicating microarchitectural ideas to RTL and circuit designers and validators. http://doi.ieeecomputersociety.org/10.1109/MDT.2011.72 http://doi.ieeecomputersociety.org/10.1109/MDT.2011.70 Evaluation of hardware Intellectual Property (IP) cores is an important step in an IP-based system-on-chip (SoC) design flow. From the perspective of both IP vendors and Integrated Circuit (IC) designers, it is desirable that hardware IPs can be freely evaluated before purchase, similar to their software counterparts. However, protection of these IPs against piracy during evaluation is a major concern for the IP vendors. Existing solutions typically use encryption and vendor-specific toolsets, which may be unacceptable due to lack of flexibility to use in-house or third-party design tools. We propose a novel low-cost solution for hardware IP protection during evaluation, by embedding a hardware Trojan inside an IP in the form of a finite state machine (FSM) with special structure. The Trojan disrupts the normal functional behavior of the IP on occurrence of a sequence of rare events, thereby effectively putting an “expiry date” on the usage of the IP. The Trojan is structurally and functionally obfuscated, thus protecting against potential reverse engineering efforts that target isolation of the Trojan circuit. http://doi.ieeecomputersociety.org/10.1109/MDT.2011.70 http://doi.ieeecomputersociety.org/10.1109/MDT.2011.49 Moore’s law has provided a metronome for semiconductor technology over the past four decades. However, when CMOS transistor feature size and interconnect dimensions approach their fundamental limits, aggressive scaling will no longer play a significant role in performance improvement. How should the semiconductor industry provide new value in each generation of products in such a scenario? While Moore’s law driven scaling has traditionally focused on improving computation performance (through faster clock frequencies and recently, more parallelism) and memory capacity, electronic systems of the future will provide value by being multi-functional. We envision that integrated systems of the future will perform diverse functions (in addition to traditional computation, storage and communication) such as real-time sensing, energy harvesting, and on-chip testing, to name a few. Enabling such diverse functionality with high performance, high reliability and a low energy budget in a single system requires a radical shift in the principles of system design and integration. Instead of focusing on improving the performance of traditional digital CMOS circuits or exploring nanotechnologies for Silicon and CMOS replacements, we espouse cohesive design and integration of multiple device technologies and diverse components in a single heterogeneous system that is high-performance, energy-efficient and reliable. http://doi.ieeecomputersociety.org/10.1109/MDT.2011.49