http://www.computer.org/cal en-us Wed, 4 Jan 2012 11:00:01 GMT http://csdl.computer.org/common/images/logos/cal.gif List of recently published journal articles http://www.computer.org/cal http://doi.ieeecomputersociety.org/10.1109/L-CA.2011.35 Traversing page table during virtual to physical address translation causes significant pipeline stalls when misses occur in the translation-lookaside buffer (TLB). To mitigate this penalty, we propose a fast, scalable, multi-level TLB organization that leverages page sharing behaviors and performs efficient TLB entry placement. Our proposed partial sharing TLB (PSTLB) reduces TLB misses by around 60%. PSTLB also improves TLB performance by nearly 40% compared to traditional private TLBs and 17% over the state of the art scalable TLB proposal. http://doi.ieeecomputersociety.org/10.1109/L-CA.2011.35 http://doi.ieeecomputersociety.org/10.1109/L-CA.2011.33 Computer architecture is beset by two opposing trends. Technology scaling and deep pipelining have led to high memory access latencies; meanwhile, power and energy considerations have revived interest in traditional in-order processors. In-order processors, unlike their superscalar counterparts, do not allow execution to continue around data cache misses. In-order processors, therefore, suffer a greater performance penalty in the light of the current high memory access latencies. Memory prefetching is an established technique to reduce the incidence of cache misses and improve performance. In this paper, we introduce B-Fetch, a new technique for data prefetching which combines branch prediction based lookahead deep path speculation with effective address speculation, to efficiently improve performance in in-order processors. Our results show that B-Fetch improves performance 38.8% on SPEC CPU2006 benchmarks, beating a current, state-of-the-art prefetcher design at ~1/3 the hardware overhead. http://doi.ieeecomputersociety.org/10.1109/L-CA.2011.33 http://doi.ieeecomputersociety.org/10.1109/L-CA.2011.25 Hardware acceleration is a widely accepted solution for performance and energy efficient computation because it removes unnecessary hardware for general computation while delivering exceptional performance via specialized control paths and execution units. The spectrum of accelerators available today ranges from coarse-grain off-load engines such as GPUs to fine-grain instruction set extensions such as SSE. This research explores the benefits and challenges of managing memory at the data-structure level and exposing those operations directly to the ISA. We call these instructions Abstract Datatype Instructions (ADIs). This paper quantifies the performance and energy impact of ADIs on the instruction and data cache hierarchies. For instruction fetch, our measurements indicate that ADIs can result in 21–48% and 16–27% reductions in instruction fetch time and energy respectively. For data delivery, we observe a 22–40% reduction in total data read/write time and 9–30% in total data read/write energy. http://doi.ieeecomputersociety.org/10.1109/L-CA.2011.25 http://doi.ieeecomputersociety.org/10.1109/L-CA.2011.21 State of the art fabrication technology for integrating numerous hardware resources such as Processors/DSPs and memory arrays into a single chip enables the emergence of Multiprocessor System-on-Chip (MPSoC). Stream programming paradigm based on MPSoC is highly efficient for single functionality scenario due to its dedicated and predictable data supply system. However, when memory traffic is heavily shared among parallel tasks in applications with multiple interrelated functionalities, performance suffers through task interferences and shared memory congestions which lead to poor parallel speedups and memory bandwidth utilizations. This paper proposes a framework of stream processing based on-chip data supply system for task-parallel MPSoCs. In this framework, stream address generations and data computations are decoupled and parallelized to allow full utilization of on-chip resources. Task granularities are dynamically tuned to jointly optimize the overall application performance. Experiments show that proposed framework as well as the tuning scheme are effective for joint optimization in task-parallel MPSoCs. http://doi.ieeecomputersociety.org/10.1109/L-CA.2011.21 http://doi.ieeecomputersociety.org/10.1109/L-CA.2011.36 Energy efficiency is a primary concern for microprocessor designers. One very effective approach to improving the energy efficiency is to lower chip supply voltage very near to the transistor threshold voltage. This reduces power consumption dramatically, improving energy efficiency by an order of magnitude. Low voltage operation, however, increases the effects of parameter variation resulting in significant frequency heterogeneity between otherwise identical cores. This heterogeneity severely limits the maximum frequency of the entire CMP. We present a combination of techniques aimed at reducing the effects of variation on the performance and energy efficiency of near-threshold, many-core CMPs. Dual Voltage Rail, mitigates core-to-core variation with a dual-rail power delivery system that allows post-manufacturing assignment of different supply voltages to individual cores. This speeds up slow cores by assigning them to a higher voltage and saves power on fast cores by assigning them to a lower voltage. Half-Speed Unit mitigates within-core variation by halving the frequency of select functional blocks with the goal of boosting the frequency of individual cores, thus raising the frequency ceiling for the entire CMP. Together, these variation-reduction techniques result in almost 50% improvement in CMP performance for the same power consumption over a mix of workloads. http://doi.ieeecomputersociety.org/10.1109/L-CA.2011.36 http://doi.ieeecomputersociety.org/10.1109/L-CA.2011.34 SIMD architectures are less efficient for applications with the diverse control-flow behavior, which can be mainly attributed to the requirement of identical control-flow. In this paper, we propose a novel instruction shuffle architecture that features an efficient control-flow handling mechanism. The cornerstones are composed of a shuffle source instruction buffer array and a shuffle unit. The shuffle unit can concurrently deliver instructions of multiple distinct control-flows from the instruction buffer array to eligible SIMD lanes. Our instruction shuffle scheme combines the best attributes of both the SIMD and MIMD execution paradigms. Applications with diverse control-flows are evaluated on our instruction shuffle architecture. Experimental results show that, the architecture can achieve 74% performance improvement on average, at the cost of only 5.8% area overhead introduced by the instruction shuffling mechnism. http://doi.ieeecomputersociety.org/10.1109/L-CA.2011.34 http://doi.ieeecomputersociety.org/10.1109/L-CA.2011.32 GPGPU architectures (applications) have several different characteristics compared to traditional CPU architectures (applications): highly multithreaded architectures and SIMD-execution behavior are the two important characteristics of GPGPU computing. In this paper, we propose a potential function that models the DRAM behavior in GPGPU architectures and a DRAM scheduling policy, Alpha-SJF policy to minimize the potential function. The scheduling policy essentially chooses between SJF and FR-FCFS at run-time based on the number of requests from each thread and whether the thread has a row buffer hit. http://doi.ieeecomputersociety.org/10.1109/L-CA.2011.32 http://opac.ieeecomputersociety.org/opac?year=2011&volume=10&issue=02&acronym=cal IEEE Computer Architecture Letters http://www.computer.org/portal/site/cal/ http://doi.ieeecomputersociety.org/10.1109/L-CA.2011.27 Studying the energy efficiency of large-scale computer systems requires models of the relationship between resource utilization and power consumption. Prior work on power modeling assumes that models built for a single node will scale to larger groups of machines. However, we find that inter-node variability in homogeneous clusters leads to substantially different models for different nodes. Moreover, ignoring this variability will result in significant prediction errors when scaled to the cluster level. We report on inter-node variation for four homogeneous five-node clusters using embedded, laptop, desktop, and server processors. The variation is manifested quantitatively in the prediction error and qualitatively on the resource utilization variables (features) that are deemed relevant for the models. These results demonstrate the need to sample multiple machines in order to produce accurate cluster models. http://doi.ieeecomputersociety.org/10.1109/L-CA.2011.27 http://doi.ieeecomputersociety.org/10.1109/L-CA.2011.26 A new generation of mobile applications requires reduced energy consumption without sacrificing execution performance. In this paper, we propose to respond to these conflicting demands with an innovative statically pipelined processor supported by an optimizing compiler. The central idea of the approach is that the control during each cycle for each portion of the processor is explicitly represented in each instruction. Thus the pipelining is in effect statically determined by the compiler. The benefits of this approach include simpler hardware and that it allows the compiler to perform optimizations that are not possible on traditional architectures. The initial results indicate that static pipelining can significantly reduce power consumption without adversely affecting performance. http://doi.ieeecomputersociety.org/10.1109/L-CA.2011.26 http://doi.ieeecomputersociety.org/10.1109/L-CA.2011.24 This paper presents a framework for high-level power estimation of multiprocessor systems-on-chip (MPSoC) architectures on FPGA. The technique is based on abstract execution profiles, called event signatures. As a result, it is capable of achieving good evaluation performance, thereby making the technique highly useful in the context of early system-level design space exploration. We have integrated the power estimation technique in a system-level MPSoC synthesis framework. Using this framework, we have designed a range of different candidate MPSoC architectures and compared our power estimation results to those from real measurements on a Virtex-6 FPGA board. http://doi.ieeecomputersociety.org/10.1109/L-CA.2011.24 http://doi.ieeecomputersociety.org/10.1109/L-CA.2011.23 In this paper, we propose a novel programmable functional unit (PFU) to accelerate general purpose application execution on a modern out-of-order x86 processor. Code is transformed and instructions are generated that run on the PFU using a co-designed virtual machine (Cd-VM). Results presented in this paper show that this HW/SW co-designed approach produces average speedups in performance of 29% in SPECFP and 19% in SPECINT, and up-to 55%, over modern out-of-order processor. http://doi.ieeecomputersociety.org/10.1109/L-CA.2011.23 http://doi.ieeecomputersociety.org/10.1109/L-CA.2011.22 Current technology trends indicate that power- and energyefficiency will limit chip throughput in the future. Current solutions to these problems, either in the way of programmable or fixed-function digital accelerators will soon reach their limits as microarchitectural overheads are successively trimmed. A significant departure from current computing methods is required to carry forward computing advances beyond digital accelerators. In this paper we describe how the energy-efficiency of a large class of problems can be improved by employing a hybrid of the discrete and continuous models of computation instead of the ubiquitous, traditional discrete model of computation. We present preliminary analysis of domains and benchmarks that can be accelerated with the new model. Analysis shows that machine learning, physics and up to one-third of SPEC, RMS and Berkeley suite of applications can be accelerated with the new hybrid model. http://doi.ieeecomputersociety.org/10.1109/L-CA.2011.22 http://doi.ieeecomputersociety.org/10.1109/L-CA.2011.37 The cost and power impact of suboptimal storage configurations is significant in datacenters (DCs). Designing performance, power and cost-optimized systems requires a deep understanding of target workloads, and mechanisms to effectively model different storage design choices. Traditional benchmarking is invalid in cloud data-stores, representative storage profiles are hard to obtain, while replaying applications in all storage configurations is highly impractical. However, current workload generators cannot reproduce key aspects of real application patterns (e.g., spatial/temporal locality). We propose a modeling and characterization framework for large-scale storage applications. We use a state diagram-based model, extend it to a hierarchical representation and implement a tool that consistently recreates DC application I/O loads. We present the framework and the validation process performed against ten original DC applications traces. Finally, we examine two use cases of this methodology: the benefits of SSD caching and defragmentation in enterprise storage. Since knowledge of the workload’s spatial and temporal locality is necessary to model these use cases, our framework was instrumental in quantifying their performance benefits. The proposed methodology provides detailed understanding of the storage activity of large-scale applications and enables a wide spectrum of storage studies without the requirement to access application code and full application deployment. http://doi.ieeecomputersociety.org/10.1109/L-CA.2011.37