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Published Articles >> Table of Contents >> Abstract
July-September 2004 (Vol. 1, No. 3)
pp. 179-189
An On-Chip Signal Suppression Countermeasure to Power Analysis Attacks
Girish B. Ratanpal, IEEE
Ronald D. Williams, IEEE
Travis N. Blalock, IEEE
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DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/TDSC.2004.25
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There are several attacks that exploit the presence of side channels in hardware implementations of cryptographic algorithms to extract secret data. Differential Power Analysis (DPA) and Simple Power Analysis (SPA) attacks sense the power consumption of the hardware to extract the secret cryptographic key. These attacks either directly examine the power traces or carry out statistical operations on the power traces obtained from the hardware while executing the cryptographic algorithm. This paper presents a circuit that can be added to crypto-hardware to suppress information leakage through the power supply pin side channel. We discuss the design, simulation results and the limitations of the suppression circuit. We show that this countermeasure significantly increases the number of power trace samples required to undertake a DPA attack. The countermeasure does not require any assumptions about the design of the hardware under protection.
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 Additional Information
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Index Terms- Power analysis attacks, security and protection, smartcards, code breaking, DES, VLSI.
Citation:
Girish B. Ratanpal, Ronald D. Williams, Travis N. Blalock,
"An On-Chip Signal Suppression Countermeasure to Power Analysis Attacks,"
IEEE Transactions on Dependable and Secure Computing,
vol. 01,
no. 3,
pp. 179-189,
Jul-Sept,
2004
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