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Published Articles >> Table of Contents >> Abstract
22nd IEEE VLSI Test Symposium
p. 206
BIST Technique by Equally Spaced Test Vector Sequences
S. Manich, Universitat Politècnica de Catalunya, Spain
L. Garcia, Universitat Politècnica de Catalunya, Spain
L. Balado, Universitat Politècnica de Catalunya, Spain
E. Lupon, Universitat Politècnica de Catalunya, Spain
J. Rius, Universitat Politècnica de Catalunya, Spain
R. Rodriguez, Universitat Politècnica de Catalunya, Spain
J. Figueras, Universitat Politècnica de Catalunya, Spain
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DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/VTEST.2004.1299245
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| Abstract |
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Built-in self-test (BIST) strategies require the implementation of efficient test pattern generators (TPG) in order to excite and observe the potential faults of the circuit. Arithmetic additive TPGs (AdTPG) allow the reuse of existing internal datapaths to perform this operation without a penalty in the circuit area. As in pseudo-random generators, AdTPGs need reseeding to efficiently cover hard-to-detect faults. The test vectors targeting hard-to-detect faults are often difficult to be obtained from a simple iterative addition operation. In this paper, a strategy to generate the reseeding for an AdTPG based on a standard ALU is presented. The methodology benefits from the existence of don't-cares in the test vectors and from the insertion of dummy vectors in the test sequence. Thanks to this, a reduction of the memory requirements and the test length is achieved.
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Citation:
S. Manich, L. Garcia, L. Balado, E. Lupon, J. Rius, R. Rodriguez, J. Figueras,
"BIST Technique by Equally Spaced Test Vector Sequences,"
vts,
p. 206,
22nd IEEE VLSI Test Symposium,
2004
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