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Published Articles >> Table of Contents >> Abstract
22nd IEEE VLSI Test Symposium
p. 193
Planar High Performance Ring Generators
Grzegorz Mrugalski, Mentor Graphics Corporation, Wilsonville, OR
Nilanjan Mukherjee, Mentor Graphics Corporation, Wilsonville, OR
Janusz Rajski, Mentor Graphics Corporation, Wilsonville, OR
Jerzy Tyszer, Poznan University of Technology, Poland
Full Article Text:
  
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/VTEST.2004.1299243
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| Abstract |
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The paper presents enhanced architectures of pseudo-random test pattern generators and on-chip test data decompressors based on ring generators. The new structures are aimed at improving their layout and routing properties while at the same time reducing propagation delays introduced by associated phase shifters.
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 Additional Information
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Citation:
Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer,
"Planar High Performance Ring Generators,"
vts,
p. 193,
22nd IEEE VLSI Test Symposium,
2004
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