Delay Defect Screening using Process Monitor Structures

Subhasish Mitra; Erik Volkerink; Edward J. McCluskey; Stefan Eichenberger

doi:10.1109/VTEST.2004.1299224

22nd IEEE VLSI Test Symposium, 2004. Proceedings.

Delay Defect Screening using Process Monitor Structures

Year: 2004, Pages: 43

DOI Bookmark: 10.1109/VTEST.2004.1299224

Authors

Subhasish Mitra, Intel Corporating, Sacramento, CA; Stanford University, CA
Erik Volkerink, Stanford University, CA
Edward J. McCluskey, Stanford University, CA
Stefan Eichenberger, Philips Semiconductors, Nijmegen, The Netherlands

Abstract

This paper presents delay test data collected from test chips fabricated in a 0.18μ technology. The experimental data shows that process monitor structures such as on-chip ring oscillators are effective in identifying slow parts while performing transition fault testing at frequencies slower than the rated frequency.

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Delay Defect Screening using Process Monitor Structures

Authors

Abstract

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