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Published Articles >> Table of Contents >> Abstract
21st IEEE VLSI Test Symposium
p. 325
SOC Test Scheduling Using Simulated Annealing
Wei Zou, University of Iowa
Sudhakar M. Reddy, University of Iowa
Irith Pomeranz, Purdue University
Yu Huang, Mentor Graphics Corporation
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DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/VTEST.2003.1197670
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| Abstract |
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We propose an SOC test scheduling method based on simulated annealing. In our method, the test scheduling is formulated as a two-dimensional bin packing problem (rectangle packing) and a data structure called a sequence pair is used to represent the placement of the rectangles. Simulated annealing is used to find the optimal test schedule by altering an initial sequence pair and changing the width of the core wrapper. We also propose a method of wrapper design for cores without internal scan chains. Experiments are conducted on ITC’02 benchmarks, showing that overall the proposed method provides better solutions compared to earlier methods.
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 Additional Information
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Citation:
Wei Zou, Sudhakar M. Reddy, Irith Pomeranz, Yu Huang,
"SOC Test Scheduling Using Simulated Annealing,"
vts,
p. 325,
21st IEEE VLSI Test Symposium,
2003
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