Proceedings. 21st VLSI Test Symposium, 2003.
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Abstract

We present a new automatic test configuration generation technique for manufacturing testing of interconnect network of SRAM-based FPGA architectures. The technique guarantees detection of open and bridging faults in all wiring channels and programmable switches in the interconnects. Only 8 test configurations are required to achieve 100% coverage of stuck-open, stuck-closed, open and bridging faults in the interconnects of Xilinx Virtex FPGAs.
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