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21st IEEE VLSI Test Symposium   p. 15
Test Data Compression and Test Time Reduction of Longest-Path-Per-Gate Tests based on Illinois Scan Architecture
Manish Sharma, University of Illinois at Urbana Champaign
Janak H. Patel, University of Illinois at Urbana Champaign
Jeff Rearick, Agilent Technologies

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DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/VTEST.2003.1197628
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Abstract
Localized delay defects, like resistive shorts, resistive opens, etc., can be effectively detected by testing the longest testable path through each wire (or gate) in the circuit. Such a delay test set is referred to as a longest-path-per-wire test set. In this paper we study test data volume and test application time reduction techniques for such tests based on the Illinois Scan architecture. We present a novel ATPG flow to quickly determine longest-path-per-wire test sets under constraints imposed by the Illinois scan architecture. Results of experiments on ISCAS sequential circuits are presented. On an average we achieve a test data volume reduction of 2.79X and number of test cycles reduction of 3.28X for robust path delay tests (as compared to the case without Illinois scan). The corresponding numbers for non-robust tests are 3.58X and 4.24X.
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Citation:  Manish Sharma, Janak H. Patel, Jeff Rearick, "Test Data Compression and Test Time Reduction of Longest-Path-Per-Gate Tests based on Illinois Scan Architecture," vts, p. 15,  21st IEEE VLSI Test Symposium,  2003