Enhanced Bist-Based Diagnosis of FPGAs via Boundary Scan Access

Carter Hamilton; Gretchen Gibson; Sajitha Wijesuriya; Charles Stroud

doi:10.1109/VTEST.1999.766697

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Proceedings 17th IEEE VLSI Test Symposium (Cat. No.PR00146)

Enhanced Bist-Based Diagnosis of FPGAs via Boundary Scan Access

Year: 1999, Pages: 413

DOI Bookmark: 10.1109/VTEST.1999.766697

Authors

Carter Hamilton, University of Kentucky
Gretchen Gibson, University of Kentucky
Sajitha Wijesuriya, University of Kentucky
Charles Stroud, University of Kentucky

Abstract

Four methods for accessing BIST for FPGAs via the IEEE 1149.1 standard Boundary Scan interface are presented and discussed in terms of advantages/disadvantages including their impact on test time and diagnostic resolution. These methods can be used in a variety of FPGA architectures for system level testing and diagnosis

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